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Volumn 2007, Issue , 2007, Pages

Thermal-aware scheduling for future chip multiprocessors

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[No Author keywords available]

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EID: 34250858227     PISSN: 16873955     EISSN: 16873963     Source Type: Journal    
DOI: 10.1155/2007/48926     Document Type: Article
Times cited : (31)

References (41)
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    • IBM Power5 chip: A dual-core multithreaded processor
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    • Niagara: A 32-way multithreaded Sparc processor
    • poonacha.kongetira@sun.com
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    • The energy efficiency of CMP vs. SMT for multimedia workloads
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    • (2004) Proceedings of the 18th Annual International Conference on Supercomputing (ICS '04) , pp. 196-206
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    • Debes, E.1
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    • TSIC: Thermal scheduling simulator for chip multiprocessors
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.