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Volumn , Issue , 2007, Pages 760-764

Multi-core design automation challenges

Author keywords

Design automation; Floorplanning; Multi core systems; Performance analysis; Power estimation; Thermal analysis; Verification

Indexed keywords

DESIGN AUTOMATION; MULTI CORE SYSTEMS; PERFORMANCE ANALYSIS;

EID: 34547351504     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375266     Document Type: Conference Paper
Times cited : (12)

References (11)
  • 1
    • 0036298603 scopus 로고    scopus 로고
    • J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, POWER4 system microarchitecture, IBM Journal of R&D, 46, No. 1, 2002, pp. 5-26.
    • J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, "POWER4 system microarchitecture", IBM Journal of R&D, Vol. 46, No. 1, 2002, pp. 5-26.
  • 2
    • 25844437046 scopus 로고    scopus 로고
    • B. Sinharoy, R. N. Kalla, J. M. Tendler, R. J. Eickemeyer, and J. B. Jovner. POWER5 system microarchitecture, IBM Journal of R&D, 49, No. 4/5, 2005, pp. 505-522.
    • B. Sinharoy, R. N. Kalla, J. M. Tendler, R. J. Eickemeyer, and J. B. Jovner. "POWER5 system microarchitecture", IBM Journal of R&D, Vol. 49, No. 4/5, 2005, pp. 505-522.
  • 3
    • 27344435504 scopus 로고    scopus 로고
    • D. Pham, Asano, S. Bolliger.M. Day, M.N. Hofstee, H.P. Johns, C. Kahle, J. Kameyama, A. Keaty, J. Masubuchi, Y. Riley, M. Shippy, D. Stasiak, D. Suzuoki, M. Wang, M. Warnock, J. Weitzel, S. Wendel, D. Yamazaki, T. Yazawa, K. The Design and Implementation of a First-Generation CELL Processor. In ISSCC Digest of Technical Papers. San Francisco, CA, February 2005 pp. 184-5
    • D. Pham, Asano, S. Bolliger.M. Day, M.N. Hofstee, H.P. Johns, C. Kahle, J. Kameyama, A. Keaty, J. Masubuchi, Y. Riley, M. Shippy, D. Stasiak, D. Suzuoki, M. Wang, M. Warnock, J. Weitzel, S. Wendel, D. Yamazaki, T. Yazawa, K. "The Design and Implementation of a First-Generation CELL Processor". In ISSCC Digest of Technical Papers. San Francisco, CA, February 2005 pp. 184-5
  • 7
    • 33748987343 scopus 로고    scopus 로고
    • Nagu Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann. Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems, Design Automation for Embedded Systems, 10, No. 2-3, September 2005, pp. 105-125.
    • Nagu Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann. "Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems", Design Automation for Embedded Systems, Vol. 10, No. 2-3, September 2005, pp. 105-125.
  • 9
    • 0038681988 scopus 로고    scopus 로고
    • Formal Design of Cache Memory Protocols in IBM
    • S.M. German, "Formal Design of Cache Memory Protocols in IBM.'". Formal Methods in System Design, 2003, pp. 133-141.
    • (2003) Formal Methods in System Design , pp. 133-141
    • German, S.M.1
  • 10
    • 0032377671 scopus 로고    scopus 로고
    • S. Park and D.L. Dill, Verification of Cache Coherence Protocols by Aggregation of Distributed Transactions. Theory of Computing Systems, 1998, pp. 355-376.
    • S. Park and D.L. Dill, "Verification of Cache Coherence Protocols by Aggregation of Distributed Transactions". Theory of Computing Systems, 1998, pp. 355-376.
  • 11
    • 34547282756 scopus 로고    scopus 로고
    • Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee
    • San Jose, November
    • Xiaofang Chen, Yu Yang, Ganesh Gopalakrishnan, and Ching-Tsun Chou, "Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee," Formal Methods in Computer Aided Design (FMCAD), IEEE, San Jose, November 2006, pp. 81-88.
    • (2006) Formal Methods in Computer Aided Design (FMCAD), IEEE , pp. 81-88
    • Chen, X.1    Yang, Y.2    Gopalakrishnan, G.3    Chou, C.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.