Compacting test responses for deeply embedded SoC cores

IEEE Design and Test of Computers

Volumn 20, Issue 4, 2003, Pages 22-30

  Sinanoglu, Ozgur ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER HARDWARE; FAULT TOLERANT COMPUTER SYSTEMS; HEURISTIC METHODS; PARALLEL PROCESSING SYSTEMS; SHIFT REGISTERS;

INDUSTRIAL COMPACTION CIRCUITRIES; MULTIPLE INPUT SIGNATURE REGISTERS;

INTEGRATED CIRCUIT TESTING;

EID: 0042522872     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1214349     Document Type: Article

References (12)

1. K. Chakrabarty, B.T. Murray, and J.P. Hayes, "Optimal Space Compaction of Test Responses," IEEE Trans. Computers, vol. 47, no. 11, Nov. 1998, pp. 1171-1187.
2. K. Chakrabarty, "Zero-Aliasing Space Compaction Using Linear Compactors with Bounded Overhead," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 5, May 1998, pp. 452-457.
3. B. Pouya and N. Touba, "Synthesis of Zero-Aliasing Space Elementary-Tree Space Compactors," Proc. 16th IEEE VLSI Test Symp. (VTS 98), IEEE CS Press, 1998, pp. 70-77.
4. K. Chakrabarty and J. P. Hayes, "Test Response Compaction Using Multiplexed Parity Trees," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 11, Nov. 1996, pp. 1399-1408.
5. O. Sinanoglu and A. Orailoglu, "Space and Time Compaction Schemes for Embedded Cores," Proc. Int'l Test Conf. (ITC 01), IEEE Press, 2001, pp. 571-579.
6. I. Pomeranz, S. Kundu, and S. M. Reddy, "On Output Response Compression in the Presence of Unknown Output Values," Proc. 39th Design Automation Conf. (DAC 02), ACM Press, 2002, pp. 255-258.
7. P. Wohl, J.A. Waicukauski, and T.W. Williams, "Design of Compactors for Signature Analyzers in Built-in Self-Test," Proc. Int'l Test Conf. (ITC 01), IEEE Press, 2001, pp. 54-63.
8. S. Mitra and K.S. Kim, "X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction," Proc. Int'l Test Conf. (ITC 02), IEEE Press, 2002, pp. 311-320.
9. P.H. Bardell, W.H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
10. P. Camurati et al., "Diagnosis Oriented Test Pattern Generation," Proc. 1st European Design Automation Conf. (EDAC 90), IEEE CS Press, 1990, pp. 470-474.
11. F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS 85), IEEE Press, 1985, pp. 663-666.
12. F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS 89), IEEE Press, 1989, pp. 1929-1934.