Design of compactors for signature-analyzers in built-in self-test

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 54-63

  Wohl, Peter ^a   Waicukauski, John A ^a   Williams, T W ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; DESIGN FOR TESTABILITY; PHASE SHIFT; SHIFT REGISTERS;

COMPACTORS; SIGNATURE-ANALYZERS;

ELECTRONIC DOCUMENT IDENTIFICATION SYSTEMS;

EID: 0035680657     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. Testing a microprocessor product using a signature analysis
2. A tutorial on built-in self-test, Part 1: Principles
3. Logic BIST for large industrial designs: Real issues and case studies
4. Self-testing of multichip logic modules
5. A tutorial on built-in self-test, Part 2: Applications
6. Automated synthesis of large phase shifters for built-in self-test
7. Automated synthesis of phase shifters for built-in self-test applications
8. Comparison of aliasing errors for primitive and non-primitive polynomials
9. Bounds and analysis of aliasing errors in linear feedback shift registers
10. Aliasing errors in multiple input signature analysis registers
11. Aliasing errors in linear automata used as multiple-input signature analyzers