Power dissipation of the network-on-chip in multi-processor system-on-chip dedicated for video coding applications

Journal of Signal Processing Systems

Volumn 57, Issue 2, 2009, Pages 139-153

  Milojevic, Dragomir ^a   Montperrus, Luc ^b   Verkest, Diederik ^c  

^a UNIVERSITÉ LIBRE DE BRUXELLES   (Belgium)

^b Arteris S 6 Parc Ariane Immeuble Mercur ^*  (France)

^c IMEC   (Belgium)

Author keywords

AVC H.264; Low power VLSI implementation; Multi processor systems on chip (MPSoC); Networks on chip (NoC); Real time video encoding, decoding

Indexed keywords

AVC/H.264; LOW-POWER VLSI IMPLEMENTATION; MULTI-PROCESSOR SYSTEMS-ON-CHIP (MPSOC); NETWORKS-ON-CHIP (NOC); REAL-TIME VIDEO ENCODING, DECODING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAMERAS; COMPUTER GRAPHICS; DECODING; DIGITAL DEVICES; DIGITAL TELEVISION; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; ENCODING (SYMBOLS); HAND HELD COMPUTERS; HIGH DEFINITION TELEVISION; IMAGE RESOLUTION; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; REAL TIME SYSTEMS; SYSTEMS ANALYSIS; TELEVISION BROADCASTING; VISUAL COMMUNICATION;

ROUTERS;

EID: 68949207781     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-008-0251-1     Document Type: Article

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