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Volumn 2005, Issue , 2005, Pages 82-85

Energy model of networks-on-chip and a bus

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ENERGY EFFICIENCY; ENERGY UTILIZATION; MATHEMATICAL MODELS; PACKET SWITCHING;

EID: 33749033522     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/issoc.2005.1595650     Document Type: Conference Paper
Times cited : (52)

References (12)
  • 1
    • 33847223636 scopus 로고    scopus 로고
    • http://www.smart-chips.com.
  • 2
    • 0000087207 scopus 로고
    • The semantics of a simple language for parallel programming
    • J. L. Rosenfeld, Ed. Stockholm, Sweden: North Holland, Amsterdam, Aug
    • G. Kahn, "The semantics of a simple language for parallel programming," in Information processing, J. L. Rosenfeld, Ed. Stockholm, Sweden: North Holland, Amsterdam, Aug 1974, pp. 471-475.
    • (1974) Information processing , pp. 471-475
    • Kahn, G.1
  • 3
    • 33847226086 scopus 로고    scopus 로고
    • Osyres, operating framework for re-configurable embedded systems
    • "Osyres, operating framework for re-configurable embedded systems," http://www.ti-wmc.nl.
  • 5
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new soc paradigm
    • January
    • L. Benini and G. de Micheli, "Networks on chips: A new soc paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, January 2002.
    • (2002) IEEE Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    de Micheli, G.2
  • 6
    • 84948976085 scopus 로고    scopus 로고
    • Orion: A power-performance simulator for interconnection networks
    • Istanbul, Turkey, November
    • H. Wang, X. Zhu, L.-S. Peh, and S. Malik, "Orion: A power-performance simulator for interconnection networks," in Proceedings of MICRO 35, Istanbul, Turkey, November 2002.
    • (2002) Proceedings of MICRO 35
    • Wang, H.1    Zhu, X.2    Peh, L.-S.3    Malik, S.4
  • 10
    • 33847191219 scopus 로고    scopus 로고
    • http://www.synopsys.com.
  • 11
    • 0036866915 scopus 로고    scopus 로고
    • A power-optimal repeater insertion methodology for global interconnects in nanometer designs
    • November
    • K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Transactions on Electron Devices, vol. 49, no. 11, pp. 2001-2007, November 2002.
    • (2002) IEEE Transactions on Electron Devices , vol.49 , Issue.11 , pp. 2001-2007
    • Banerjee, K.1    Mehrotra, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.