A systematic approach to design low-power video codec cores

Eurasip Journal on Embedded Systems

Volumn 2007, Issue , 2007, Pages

  Denolf, Kristof ^a   Chirila Rus, Adrian ^b   Schumacher, Paul ^b   Turney, Robert ^b   Vissers, Kees ^b   Verkest, Diederik ^a,c,d   Corporaal, Henk ^e  

^a IMEC   (Belgium)

^b XILINX INC   (United States)

^c Katholieke Universiteit Leuven   (Belgium)

^d VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^e EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 34250842558     PISSN: 16873955     EISSN: 16873963     Source Type: Journal    
DOI: 10.1155/2007/64569     Document Type: Article

References (52)

1. M. A. Viredaz viredaz@computer.org D. A. Wallach kerr@alum.mit.edu Power evaluation of a handheld computer. IEEE Micro 23 1 2003 66 74
2. A. Lambrechts arpa@imec.be P. Raghavan arpa@imec.be A. Leroy arpa@imec.be Power breakdown analysis for a heterogeneous NoC platform running a video application. Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP '05) 2005 Samos, Greece 179 184
3. T. Fujiyoshi S. Shiratake S. Nomura A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic voltage/frequency scaling. IEEE Journal of Solid-State Circuits 41 1 2006 54 62
4. M. Horowitz E. Alon D. Patil S. Naffziger R. Kumar K. Bernstein Scaling, power, and the future of CMOS. Proceedings of IEEE International Electron Devices Meeting (IEDM '05) Washington, DC, USA 2005 7
5. G. Bilsen M. Engels R. Lauwereins J. Peperstraete Cyclo-static dataflow. IEEE Transactions on Signal Processing 44 2 1996 397 408
6. P. Pirsch M. Berekovic H.-J. Stolberg J. Jachalsky VLSI architectures for MPEG-4. Proceedings of International Symposium on VLSI Technology, Systems, and Applications (VTSA '03) Hsinchu, Taiwan 2003 208A 208E
7. S.-Y. Chien sychien@cc.ee.ntu.edu.tw Y.-W. Huang C.-Y. Chen H. H. Chen L.-G. Chen Hardware architecture design of video compression for multimedia communication systems. IEEE Communications Magazine 43 8 2005 123 131
8. C.-J. Lian Y.-W. Huang H.-C. Fang Y.-C. Chang L.-G. Chen lgchen@cc.ee.ntu.edu.tw JPEG, MPEG-4, and H.264 codec IP development. Proceedings of Design, Automation and Test in Europe (DATE '05) 2 Munich, Germany 2005 1118 1119
9. S. Edwards sedwards@berkely.edu L. Lavagno luciano@cadence.com E. A. Lee eal@eecs.berkeley.edu A. Sangiovanni-Vincentelli alberto@leonardo.Darades.rm. cnr.it Design of embedded systems: formal models, validation, and synthesis. Proceedings of the IEEE 85 3 1997 366 390
10. L. Mazzoni Power aware design for embedded systems. IEE Electronics Systems and Software 1 5 2003 12 17
11. F. Catthoor S. Wuytack E. de Greef F. Balasa L. Nachtergaele A. Vandecappelle Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design. Kluwer Academic Publishers Norwell, Mass, USA 1998
12. P. R. Panda panda@synopsys.com F. Catthoor catthoor@imec.be N. D. Dutt dutt@cecs.uci.edu Data and memory optimization techniques for embedded systems. ACM Transactions on Design Automation of Electronic Systems 6 2 2001 149 206
13. K. Denolf ristof.denolf@imec.be C. de Vleeschouwer devlees@tele.ucl.ac.be R. Turney G. Lafruit gauthier.lafruit@imec.be J. Bormans jan.bormans@imec.be Memory centric design of an MPEG-4 video encoder. IEEE Transactions on Circuits and Systems for Video Technology 15 5 2005 609 619
14. E. A. Lee T. M. Parks Dataflow process networks. Proceedings of the IEEE 83 5 1995 773 801
15. A. Davare davare@eecs.berkeley.edu Q. Zhu zhuqi@eecs.berkeley.edu J. Moondanos john.moondanos@intel.com A. Sangiovanni-Vincentelli alberto@eecs.berkeley.edu JPEG encoding on the Intel MXP5800: a platform-based design case study. Proceedings of the 3rd IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTImedia '05) New York, NY, USA 2005 89 94
16. H. Hwang hyhwang@iris.snu.ac.kr T. Oh twoh@iris.snu.ac.kr H. Jung jung@iris.snu.ac.kr S. Ha sha@iris.snu.ac.kr Conversion of reference C code to dataflow model: H.264 encoder case study. Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '06) Yokohama, Japan 2006 152 157
17. F. Haim M. Sen D.-I. Ko S. S. Bhattacharyya W. Wolf Mapping multimedia applications onto configurable hardware with parameterized cyclo-static dataflow graphs. Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '06) 3 Toulouse, France 2006 1052 1055
18. M. C. Williamson E. A. Lee Synthesis of parallel hardware implementations from synchronous dataflow graph specifications. Proceedings of the 30th Asilomar Conference on Signals, Systems and Computers 2 Pacific Grove, Calif, USA 1996 1340 1343
19. J. Horstmannshoff H. Meyr Efficient building block based RTL code generation from synchronous data flow graphs. Proceedings of the 37th Conference on Design Automation (DAC '00) 2000 Los Angeles, Calif, USA 552 555
20. H. Jung jung@iris.snu.ac.kr K. Lee knlee@iris.snu.ac.kr S. Ha sha@iris.snu.ac.kr Efficient hardware controller synthesis for synchronous dataflow graph in system level design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 4 2002 423 428
21. J. Dalcolmo R. Lauwereins M. Ade Code generation of data dominated DSP applications for FPGA targets. Proceedings of the 9th IEEE International Workshop on Rapid System Prototyping 1998 Leuven, Belgium 162 167
22. R. Grou-Szabo grow@grm.polymtl.ca H. Ghattas ghattas@grm.polymtl.ca Y. Savaria savaria@grm.polymtl.ca G. Nicolescu gabriela.nicolescu@polymtl.ca Component-based methodology for hardware design of a dataflow processing network. Proceedings of the 5th International Workshop on System-on-Chip for Real-Time Applications (IWSOC '05) Banff, Alberta, Canada 2005 289 294
23. K. Keutzer A. R. Newton J. M. Rabaey A. Sangiovanni-Vincentelli System-level design: orthogonalization of concerns and platform-based design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19 12 2000 1523 1543
24. D. Denning N. Harold M. Devlin J. Irvine Using system generator to design a reconfigurable video encryption system. Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL '03) Lisbon, Portugal 2003 980 983
25. Y. Nakamura yuichi@az.jp.nec.com K. Hosokawa k-hosokawa@da.jp.nec.com I. Kuroda kuroda@ah.jp.nec.com K. Yoshikawa k-yoshikawa@bx.jp.nec.com T. Yoshimura t-yoshimura@waseda.jp A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. Proceedings of the 41st Design Automation Conference (DAC '04) San Diego, Calif, USA 2004 299 304
26. R. Siripokarpirom siripokarpirom@tuhh.de F. Mayer-Lindenberg Hardware-assisted simulation and evaluation of IP cores using FPGA-based rapid prototyping boards. Proceedings of the 15th IEEE International Workshop on Rapid Systems Prototyping 2004 Geneva, Switzerland 96 102
27. I. Amer M. Sayed W. Badawy G. Jullien On the way to an H.264 HW/SW reference model: a systemC modeling strategy to integrate selected IP-blocks with the H.264 software reference model. Proceedings of IEEE Workshop on Signal Processing Systems Design and Implementation (SIPS '05) Athens, Greece 2005 178 181
28. I. Amer iamer@ucalgary.ca C. A. Rahman carahman@ucalgary.ca T. Mohamed tsemohamed@ucalgary.ca M. Sayed msayed@ucalgary.ca W. Badawy badawy@ucalgary.ca A hardware-accelerated framework with IP-blocks for application in MPEG-4. Proceedings of the 5th International Workshop on System-on-Chip for Real-Time Applications (IWSOC '05) Banff, Alberta, Canada 2005 211 214
29. M. J. Irwin M. T. Kandemir N. Vijaykrishnan A. Sivasubramaniam A holistic approach to system level energy optimization. Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation (PATMOS '00) Göttingen, Germany Springer 2000 88 107
30. http://www.imec.be/design/atomium/
31. P. Schumacher K. Denolf A. Chirila-Rus A scalable, multi-stream MPEG-4 video decoder for conferencing and surveillance applications. Proceedings of IEEE International Conference on Image Processing (ICIP '05) 2 Genova, Italy 2005 886 889
32. Information technology - generic coding of audio-visual objects - part 2: visual. ISO/IEC 14496-2:2004, June 2004
33. V. Bhaskaran K. Konstantinides Image and Video Compression Standards, Algorithms and Architectures. Kluwer Academic Publishers Boston, Mass, USA 1997
34. Information technology - generic coding of audio-visual objects - part 5: reference software. ISO/IEC 14496-5:2001, December 2001
35. C. de Vleeschouwer devlees@tele.ucl.ac.be Model-based rate control implementation for low-power video communications systems. IEEE Transactions on Circuits and Systems for Video Technology 13 12 2003 1187 1194
36. C. de Vleeschouwer devlees@tele.ucl.ac.be T. Nilsson K. Denolf J. Bormans Algorithmic and architectural co-design of a motion-estimation engine for low-power video devices. IEEE Transactions on Circuits and Systems for Video Technology 12 12 2002 1093 1105
37. S. Sriram S. S. Bhattacharyya Embedded Multiprocessors: Scheduling and Synchronization. Marcel Dekker New York, NY, USA 2000
38. M. Wiggers M. Bekooij P. Jansen G. Smit Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure. Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) Seoul, Korea 2006 10 15
39. T. Rintaluoma O. Silven J. Raekallio Interface overheads in embedded multimedia software. Proceedings of the 6th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS '06) Samos, Greece 2006 5 14
40. Amphion Standalone MPEG-4 video encoders. 2003 CS6701 product specification
41. H. Nakayama T. Yoshitake H. Komazaki An MPEG-4 video LSI with an error-resilient codec core based on a fast motion estimation algorithm. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '02) 2002 San Francisco, Calif, USA 1 368 474
42. T. Yamada N. Irie J. Nishimoto A 133 MHz 170 mW 10 μA standby application processor for 3G cellular phones. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '02) 2002 1 San Francisco, Calif, USA 370 474
43. H. Arakida M. Takahashi Y. Tsuboi A 160 mW, 80 nA standby, MPEG-4 audiovisual LSI with 16 Mb embedded DRAM and a 5 GOPS adaptive post filter. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '03) 1 San Francisco, Calif, USA 2003 42 476
44. Y.-C. Chang W.-M. Chao L.-G. Chen Platform-based MPEG-4 video encoder SOC design. Proceedings of IEEE Workshop on Signal Processing Systems Design and Implementation (SIPS '04) 2004 Austin, Tex, USA 251 256
45. H. Yamauchi S. Okada T. Watanabe An 81MHz, 1280 × 720pixels × 30frames/s MPEG-4 video/audio codec processor. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '05) 1 San Francisco, Calif, USA 2005 130 589
46. Y. Watanabe T. Yoshitake K. Morioka Low power MPEG-4 ASP codec IP macro for high quality mobile video applications. Proceedings of IEEE International Conference on Consumer Electronics (ICCE '05) 2005 Las Vegas, Nev, USA 337 338
47. C.-P. Lin P.-C. Tseng Y.-T. Chiu A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications. Proceedings of IEEE International Solid-State Circuits Conference (ISSCC '06) San Francisco, Calif, USA 2006 1 1626 1635
48. http://www.annapmicro.com/products.html
49. ISO/IEC JTC1/SC29WG11 Information technology - generic coding of audio-visual objects - part 2: visual, amendment 2: new levels for simple profile. N6496 Redmond, USA 2004
50. http://www.synopsys.com/
51. http://www.model.com/
52. http://www.itrs.net/Links/2006Update/FinalToPost/02_Design_2006Update.pdf