A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 1, 2006, Pages 54-62

  Fujiyoshi, T ^a   Shiratake, S ^a   Nomura, S ^a   Nishikawa, T ^a   Kitasho, Y ^a   Arakida, H ^a   Okuda, Y ^a   Tsuboi, Y ^a   Hamada, M ^a   Hara, H ^a   Fujita, T ^a   Hatori, F ^a   Shimazawa, T ^a   Yahagi, K ^a   Takeda, H ^a   Murakata, M ^a   Minami, F ^a   Kawabe, N ^a   Kitahara, T ^a   Seta, K ^a   Takahashi, M ^a   Oowaki, Y ^a   Furuyama, T ^a   more..

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Audio codec LSI; Dynamic deskewing system; Dynamic voltage frequency scaling architecture; H.264; Low power techniques; Mobile applications; MPEG 4; On chip voltage regulator; Slew rate control; Terrestrial digital broadcasting system; Visual codec LSI

Indexed keywords

AUDIO SYSTEMS; BROADCASTING; DIGITAL COMMUNICATION SYSTEMS; ELECTRIC POTENTIAL; VISUAL COMMUNICATION;

AUDIO CODEC LSI; DYNAMIC DESKEWING SYSTEM; DYNAMIC VOLTAGE-FREQUENCY SCALING ARCHITECTURE; H.264; MOBILE APPLICATIONS; MPEG-4; ON CHIP VOLTAGE REGULATOR; SLEW RATE CONTROL; TERRESTRIAL DIGITAL BROADCASTING SYSTEM; VISUAL CODEC LSI;

MOBILE TELECOMMUNICATION SYSTEMS;

EID: 31344463250     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.859337     Document Type: Article

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