Process control for 45 nm CMOS logic gate patterning

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6922, Issue , 2008, Pages

  Le Gratiet, Bertrand ^a   Gouraud, Pascal ^a   Aparicio, Enrique ^a   Babaud, Laurene ^a   Dabertrand, Karen ^a   Touchet, Mathieu ^a   Kremer, Stephanie ^c   Chaton, Catherine ^b   Foussadier, Franck ^a   Sundermanna, Frank ^a   Massin, Jean ^a   Chapon, Jean Damien ^a   Gatefait, Maxime ^a   Minghetti, Blandine ^a   De Caunes, Jean ^a   Boutin, Daniel ^a  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

^c KLA TENCOR CORPORATION   (United States)

Author keywords

45nm logic gate; CD uniformity; Immersion lithography; Scatterometry

Indexed keywords

45NM LOGIC GATE; CD BUDGET; CD CONTROL; CD UNIFORMITY; CMOS LOGIC GATES; GATE PATTERNING PROCESS; IMMERSION LITHOGRAPHY; INTRAFIELD; PRODUCTION ENVIRONMENTS; SCATTEROMETRY;

LITHOGRAPHY; LOGIC GATES; UNITS OF MEASUREMENT;

PROCESS CONTROL;

EID: 57849123487     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.776889     Document Type: Conference Paper

References (5)

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