Scalability of strained nitride capping layers for future CMOS generations

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 449-452

  Eneman, G ^a,b,c   Jurczak, M ^a   Verheyen, P ^a   Hoffmann, T ^a   De Keersgieter, A ^a   De Meyer, K ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c FUND FOR SCIENTIFIC RESEARCH   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LINES; NITRIDES; STRESS ANALYSIS;

CMOS GENERATIONS; NITRIDE CAPPING LAYERS; TRANSISTOR CHANNELS;

CMOS INTEGRATED CIRCUITS;

EID: 33744832246     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546681     Document Type: Conference Paper

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