Across wafer critical dimension uniformity enhancement through lithography and etch process sequence: Concept, approach, modeling, and experiment

IEEE Transactions on Semiconductor Manufacturing

Volumn 20, Issue 4, 2007, Pages 488-505

  Zhang, Qiaolin ^a,b   Poolla, Kameshwar ^a   Spanos, Costas J ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SYNOPSYS INC   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CD UNIFORMITIES; CD VARIATIONS; CHIP PERFORMANCE; CRITICAL DIMENSION UNIFORMITIES; ETCH PROCESS; PEB TEMPERATURES; PERFORMANCE SPECIFICATIONS; POST-EXPOSURE BAKE TEMPERATURES; SCANNING ELECTRON MICROSCOPES; SET POINTS; STANDARD DEVIATIONS;

SCANNING ELECTRON MICROSCOPY; TEMPERATURE CONTROL;

DATA STORAGE EQUIPMENT;

EID: 64349103196     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2007.907627     Document Type: Article

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