Analog/RF performance of multichannel SOI MOSFET

IEEE Transactions on Electron Devices

Volumn 56, Issue 7, 2009, Pages 1473-1482

  Lim, Tao Chuan ^a   Bernard, Emilie ^b,c   Rozeau, Olivier ^c   Ernst, Thomas ^c   Guillaumot, Bernard ^b,c   Vulliet, Nathalie ^b,c   Buj Dufournet, Christel ^c   Paccaud, Michel ^c   Lepilliet, Sylvie ^a   Dambrine, Gilles ^a,d   Danneville, François ^a,d  

^a INSTITUT D ELECTRONIQUE   (France)

^b MINATEC   (France)

^c STMICROELECTRONICS   (Italy)

^d UNIV LILLE   (France)

Author keywords

Early voltage; High frequency (HF); Multichannel MOSFET; Silicon; Silicon on insulator (SOI); Voltage gain

Indexed keywords

CAPACITANCE; GAIN MEASUREMENT; MOSFET DEVICES; SCATTERING PARAMETERS; SILICON; SILICON ON INSULATOR TECHNOLOGY;

EARLY VOLTAGE; HIGH FREQUENCY HF; MOS-FET; SILICON ON INSULATOR (SOI); VOLTAGE GAIN;

SILICON WAFERS;

EID: 67650140661     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2021438     Document Type: Article

References (28)

1. S. J. Lee, L. Wagner, B. Jagannathan, S. Csutak, J. Pekarik, N. Zamdmer, M. Breitwisch, R. Ramachrandran, and G. Freeman, "Record RF performance of sub-46 nm L/sub gate/NFETs in microprocessor SOI CMOS technologies," in IEDM Tech. Dig., Dec. 5-7, 2005, pp. 241-244.
2. S. J. Lee, J. H. Kim, D. Kim, B. Jagannathan, C. Cho, J. Johnson, B. Dufrene, N. Zamdmer, L. Wagner, R. Williams, D. Fried, R. Ken, J. Pekarik, S. Springer, J.-O. Plouchart, and G. Freeman, "SOI CMOS technology with 360 GHz fT NFET, 260 GHz fT PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications," in VLSI Symp. Tech. Dig., Jun. 12-14, 2007, pp. 54-55.
3. S. J. Lee, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams, L. Wagner, J. Kim, J.-O. Plouchart, J. Pekarik, S. Springer, and G. Freeman, "Record RF performance of 45-nm SOI CMOS technology," in IEDM Tech. Dig., Dec. 10-14, 2007, pp. 255-258.
4. F. Andrieu, O. Faynot, F. Rochette, J.-C. Barbe, C. Buj, Y. Bogumilowicz, F. Allain, V. Delaye, D. Lafond, F. Aussenac, S. Feruglio, J. Eymery, T. Akatsu, P. Maury, L. Brevard, L. Tosti, H. Dansas, E. Rouchouze, J.-M. Hartmann, L. Vandroux, M. Casse, F. Boeuf, C. Fenouillet-Beranger, F. Brunier, I. Cayrefourcq, C. Mazure, G. Ghibaudo, and S. Deleonibus, "Impact of mobility boosters (XsSOI, CESL, TiN gate) on the performance of g2 100 g4 or g2 100 g4 oriented FDSOI cMOSFETs for the 32 nm node," in VLSI Symp. Tech. Dig., Jun. 12-14, 2007, pp. 50-51.
5. 2 6T-SRAM bitcell," in IEDM Tech. Dig., Dec. 10-12, 2007, pp. 267-270.
6. 2 gate stack," in ULIS, Mar. 12-14, 2008, pp. 145-148.
7. J. Widiez, F. Dauge, M. Vinet, T. Poiroux, B. Previtali, M. Mouis, and S. Deleonibus, "Experimental gate misalignment analysis on double gate SOI MOSFETs," in IEEE SOI Conf., Oct. 4-7, 2004, pp. 185-186.
8. J. Widiez, J. Lolivier, M. Vinet, T. Poiroux, B. Previtali, F. Dauge, M. Mouis, and S. Deleonibus, "Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1772-1779, Aug. 2005.
9. T. C. Lim, A. Kranti, and A. Armstrong, "Performance assessment of nanoscale multiple gate MOSFETs (MuGFETs) for RF applications," in Eur. Microw. Integr. Circuit Conf., EuMIC, Oct. 2006, pp. 141-142.
10. D. Lederer, B. Parvais, A. Mercha, N. Collaert, M. Jurczak, J.-P. Raskin, and S. Decoutere, "Dependence of FinFET RF performance on fin width," in Proc. Silicon Monolithic Integr. Circuits RF Syst., 2006, pp. 8-11.
11. V. Subramanian, B. Parvais, J. Borremans, A. Mercha, D. Linten, P. Wambacq, J. Loo, M. Dehan, C. Gustin, N. Collaert, S. Kubicek, R. Lander, J. Hooker, F. Cubaynes, S. Donnay, M. Jurczak, G. Groeseneken, W. Sansen, and S. Decoutere, "Planar bulk MOSFETs versus FinFETs: An analog/RF perspective," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3071-3079, Dec. 2006.
12. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. De Meyer, "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132-1140, Jun. 2005.
13. J. Raskin, T. M. Chung, V. Kilchytska, D. Lederer, and D. Flandre, "Analog/RF performance of multiple gate SOI devices: Wideband simulations and characterization," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1088-1095, May 2006.
14. E. Baravelli, M. Jurczak, N. Speciale, K. De Meyer, and A. Dixit, "Impact of LER and random dopant fluctuations on FinFET matching performance," IEEE Trans. Nanotechnol., vol. 7, no. 3, pp. 291-298, May 2008.
15. S.-Y. Lee, S.-M. Kim, E.-J. Yoon, C.-W. Oh, I. Chung, D. Park, and K. Kim, "Three-dimensional MBCFET as an ultimate transistor," IEEE Electron Device Lett., vol. 25, no. 4, pp. 217-219, Apr. 2004.
16. E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, X. Garros, V. Maffini-Alvaro, P. Coronel, T. Skotnicki, and S. Deleonibus, "Impact of gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI," Solid State Electron., vol. 52, no. 9, pp. 1297-1302, Sep. 2008.
17. E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, V. Maffini-Alvaro, F. Andrieu, G. LeCarval, P. Vizioz, Y. Campidelli, O. Kermarrec, J. M. Hartmann, S. Borel, V. Delaye, A. Pouydebasque, A. Souifi, P. Coronel, T. Skotnicki, and S. Deleonibus, "3D stacked channels: How series resistances can limit 3D devices performance," in IEEE SOI Conf., Oct. 1-4, 2007, pp. 93-94.
18. E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, V. Barral, V. Maffini-Alvaro, F. Andrieu, C. Vizioz, Y. Campidelli, P. Gautier, J. M. Hartmann, R. Kies, V. Delaye, F. Aussenac, T. Poiroux, P. Coronel, A. Souifi, T. Skotnicki, and S. Deleonibus, "Novel integration process and performances analysis of Low STandby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) on SOI with metal/high-κ gate stack," in VLSI Symp. Tech. Dig., Jun. 17-19, 2008, pp. 16-17.
19. T. Ernst, E. Bernard, C. Dupré, A. Hubert, S. Bécu, B. Guillaumot, O. Rozeau, O. Thomas, P. Coronel, J.-M. Hartmann, C. Vizioz, N. Vulliet, O. Faynot, T. Skotnicki, and S. Deleonibus, "3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics," in Int. Conf. IC Design Technol., Jun. 2-4, 2008, pp. 265-268.
20. 2 gate multi-channel MOSFET satisfying both high performance and low standby power requirements," IEEE Electron Device Lett., vol. 30, no. 2, pp. 148-151, Feb. 2009.
21. International Technology Roadmap for Semiconductors. [Online]. Available: http://www.itrs.net/links/2005ITRS/Home2005.htm
22. V. P. Trivedi and J. G. Fossum, "Source/drain-doping considerations for nanoscale FinFET design," in IEEE SOI Conf., Oct. 4-7, 2004, pp. 192-194.
23. T. C. Lim and G. A. Armstrong, "Parameter sensitivity for optimal design of 65 nm node double gate SOI transistors," Solid State Electron., vol. 49, no. 6, pp. 1034-1043, Jun. 2005.
24. Rashmi, A. Kranti, and G. A. Armstrong, "6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: Impact of source/drain engineering and circuit topology," Semicond. Sci. Technol., vol. 23, no. 7, pp. 1-13, Jul. 2008.
25. A. Kranti and G. A. Armstrong, "Source/drain extension region engineering in FinFETs for low-voltage analog applications," IEEE Electron Device Lett., vol. 28, no. 2, pp. 139-141, Feb. 2007.
26. T. C. Lim and G. A. Armstrong, "The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance," Solid State Electron., vol. 50, no. 5, pp. 774-783, May 2006.
27. A. Kranti and G. A. Armstrong, "Design and optimization of FinFETs for ultra-low-voltage analog applications," IEEE Trans. Electron Devices vol. 54, no. 12, pp. 3308-3316, Dec. 2007.
28. ATLAS User's Manual, SILVACO Int., Santa Clara, CA, Dec. 2005. vet. 5.10.2.R.