3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics

Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2008, Pages 265-268

  Ernst, T ^a,b   Bernard, E ^b   Dupre C ^b   Hubert, A ^b   Becu S ^b   Guillaumot, B ^c   Rozeau, O ^b   Thomas, O ^b   Coronel, P ^c   Hartmann, J M ^b   Vizioz, C ^b   Vulliet, N ^c   Faynot, O ^a,b   Skotnicki, T ^a,c   Deleonibus, S ^a,b  

^a IEEE

^b CEA LETI   (France)

^c STMICROELECTRONICS   (France)

Author keywords

CMOS; CMOS scaling; FinFET; Multichannel; PhiFET

Indexed keywords

ELECTRIC WIRE; ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT MANUFACTURE; MOSFET DEVICES; TECHNOLOGY;

32NM NODES; CMOS; CMOS DEVICES; CMOS SCALING; FINFET; INTEGRATED CIRCUIT DESIGN; INTERNATIONAL CONFERENCES; LOW LEAKAGE; MULTI-CHANNELS; MULTICHANNEL; NEW DESIGN; PHIFET; SPECIFIC ADVANTAGES; STACKED GATE;

INTEGRATED CIRCUITS;

EID: 51849161404     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2008.4567292     Document Type: Conference Paper

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