System-level PVT variation-aware power exploration of on-chip communication architectures

ACM Transactions on Design Automation of Electronic Systems

Volumn 14, Issue 2, 2009, Pages

  Pasricha, Sudeep ^a,c   Park, Young Hwan ^b   Dutt, Nikil ^b   Kurdahi, Fadi J ^b  

^a Veterinary Dentistry and Oral Surgery   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Department of Mechanical Engineering   (United States)

Author keywords

Digital systems; High level synthesis; On chip communication architectures; Performance exploration; Power estimation; PVT variation

Indexed keywords

DIGITAL SYSTEMS; HIGH-LEVEL SYNTHESIS; ON-CHIP COMMUNICATION ARCHITECTURES; PERFORMANCE EXPLORATION; POWER ESTIMATION; PVT VARIATION;

ABSTRACTING; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION; ELECTRIC POWER UTILIZATION; ESTIMATION; PROGRAMMABLE LOGIC CONTROLLERS;

MICROPROCESSOR CHIPS;

EID: 65849368968     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1497561.1497563     Document Type: Article

References (32)

1. ADYA, S. N. AND MARKOV, I. L. 2003. Fixed-outline floorplanning: Enabling hierarchical design. IEEE Trans. VLSI Syst. 11, 6, 1120-1135.
2. AMBA AHB Interconnection Matrix. 2008. http://www.synopsys.com/products/ designware/ambasolutions.html.
3. BANERJEE, K. AND MEHROTRA, A. 2001. Coupled analysis of electromigration reliability and performance in ULSI signal nets. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 158-164.
4. BENINI, L., MACII, A., PONCINO, M., AND SCARSI, R. 2000. Architectures and synthesis algorithms for power-efficient bus interfaces. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 19, 9, 969-980.
5. BONA, A., ZACCARIA, V., AND ZAFALON, R. 2004. System level power modeling and simulation of high-end industrial network-on-chip. In Proceedings of the Conference on Design, Automation and Test in Europe.
6. st Design Automation Conference. 75.
7. CADENCE PKS. 2008. www.cadence.com/datasheets/pksds.pdf.
8. CALDARI, M., CONTI, M., COPPOLA, M., CRIPPA, P., ORCIONI, S., PIERALISI, L., AND TURCHETTI, C. 2003. System-level power analysis methodology applied to the AMBA AHB bus. In Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum.
9. DHANWADA, N., LIN, I., AND NARAYANAN, V. 2005. A power estimation methodology for system C transaction level models. In Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
10. FARAWAY, J. J. 2004. Linear Models with R. CRC Press.
11. GNU R. 2008. http://www.gnu.org/software/r/R.html.
12. Ho, R., MAI, K. W., AND HOROWITZ, M. A. 2001. The future of wires. Proc. IEEE 89, 4, 490-504. (Pubitemid 33766588)
13. JVTISO/IEC MPEG, ITU-T VCEG. 2003. Final draft international standard of joint video specificati on (ITU-T Rec. H.264/ISO/IEC 14496-10 AVC). JVT-G050.
14. KHANDELWAL, V. AND SRIVASTAVA, A. 2005. A general framework for accurate statistical timing analysis considering correlations. In Proceedings of the 42nd Design Automation Conference. 89-94.
15. KRETZSCHMAR, C., NIEUWLAND, A. K., AND MÜLLER, D. 2004. Why transition coding for power minimization of on-chip buses does not work. In Proceedings of the Conference on Design, Automation and Test in Europe.
16. LAHIRI, K. AND RAGHUNATHAN, A. 2004. Power analysis of system-level on-chip communication architectures. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS). 236-241.
17. LAHIRI, K., RAGHUNATHAN, A., DEY, S., AND PANIGRAHI, D. 2002. Battery-driven system design: A new frontier in low power design. In Proceedings of ASP-DAC 7th Asia and South Pacific Design Automation Conference and Proceedings of the 15th International Conference on VLSI Design. 261-267.
18. LAJOLO, M., RAGHUNATHAN, A., DEY, S., AND LAVAGNO, L. 2002. Cosimulation-based power estimation for system-on-chip design. IEEE Trans. VLSI Syst. 10, 3, 253-266. (Pubitemid 35369645)
19. st Design Automation Conference. 343-348.
20. LEE, I., Kim, H., YANG, P., Yoo, S., CHUNG, E., CHOI, K., KONG, J., AND EO, S. 2006. PowerViP: SoC power estimation framework at transaction level. In Proceedings of the Asia and South Pacific Conference on Design Automation. 24-27. (Pubitemid 44375988)
21. METRO IP. http://www.arm.com/products/physicalip/metro.html.
22. PASRICHA, S. 2002. Transaction level modeling of SoC with System C 2.0. In Proceedings of the SNUG Conference.
23. PASRICHA, S. AND DUTT, N 2008. On-Chip Communication Architectures. Morgan Kaufmann/Elsevier.
24. PASRICHA, S., DUTT, N., AND BEN-ROMDHANE, M. 2004. Extending the transaction level modeling approach for fast communication architecture exploration. In Proceedings of the 41st Annual Conference on Design Automation. 113-118.
25. th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). ACM, 300-305.
26. RABAEY, J., CHANDRAKASAN, A., AND NIKOLIC, B. 2003. Digital Integrated Circuits: A Design Perspective2nd Ed. Prentice-Hall, Englewood Cliffs, NJ.
27. RAGHUNANDAN, C., SAINARAYANAN, K. S., AND SRINIVAS, M. B. 2008. Process variation aware bus-coding scheme for delay minimization in VLSI interconnects. In Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED). 43-46.
28. SOTIRIADIS, P. P. AND CHANDRAKASAN, A. P. 2002. A bus energy model for deep submicron technology. IEEE Trans. Very VLSI Systems 10, 3, 341-350. (Pubitemid 35369653)
29. SYNOPSYS CORETOOLS, PRIMETIME PX. 2008. http://www.synopsys.com.
30. SYSTEMC INITIATIVE. 2008. http://www.systemc.org.
31. TUUNA, S., ISOAHO, J., AND TENHUNEN, H. 2008. Analysis of delay variation in encoded on-chip bus signaling under process variation. In Proceedings of the 21st International Conference on VLSI Design. 228-234.
32. WANG, H., MIRANDA, M., LOBMAIER, F., CATTHOOR, F., AND PAPANIKOLAOU, A. 2005. A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications. In Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). 117-122.