A power estimation methodology for SystemC transaction level models

CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2005, Pages 142-147

  Dhanwada, Nagu ^a   Lin, Ing Chao ^b   Narayanan, Vijay ^b  

^a IBM   (United States)

^b The Pennsylvania State University   (United States)

Author keywords

CoreConnect; Power Analysis; PowerPC; SystemC; Transaction Level Models

Indexed keywords

ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; MATHEMATICAL MODELS; PERSONAL COMPUTERS;

CORECONNECT; POWER ANALYSIS; POWERPC; SYSTEMC; TRANSACTION LEVEL MODELS;

MICROPROCESSOR CHIPS;

EID: 27644585187     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1084834.1084874     Document Type: Conference Paper

References (11)

1. R. A. Bergamaschi, Y. Shin, N. Dhanwada, S. Bhattacharya, W E. Dougherty, I. Nair, J. Darringer, S. Paliwal "SEAS: A System for Early Analysis of SoCs", Proc. CODES/ISSS 2003
2. M. Caldari, M. Conti, M. Coppola, P. Crippa, S. Orcioni, L. Pieralisi, and C. Turchetti, "System-Level Power Analysis Methodology Applied to the AMBA AHB Bus", DATE 2003.
3. "The Open SystemC Initiative." http://www.systemc.org.
4. th ISSS.
5. G. Qu, N. Kawabe, K, Usame, M. Potkonjak, Function-level power estimation methodology for microprocessors, Proceedings of the 37th DAC, 2000.
6. th Design Automation Conference, 2003.
7. The CoreConnect Bus Architecture", available at http://www.chips. ibm.com/products/coreconnect.
8. R. Devins, "SoC Verification Software - Test Operating System", IEEE/DATC Electronic Design Processes Workshop, April 2001
9. M. Burton, A. Donlin, "Transaction-Level Modeling: Above RTL Design and Methodology", http://www.systemc.org.
10. T. Grötker, S. Liao, G. Martin, S. Swan, "System Design with SystemC", Kluwer Academic Publishers, 2002.
11. L. Zhong, S. Ravi, A. Raghunathan, N. K. Jha. "Power Estimation for Cycle-Accurate Functional Descriptions of Hardware", ICCAD 2004.