System-level power-performance trade-offs in bus matrix communication architecture synthesis

CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis

Volumn , Issue , 2006, Pages 300-305

  Pasricha, Sudeep ^a   Park, Young Hwan ^a   Kurdahi, Fadi J ^a   Dutt, Nikil ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Bus matrix synthesis; Communication architectures; Power estimation; Power performance trade offs; System on chip

Indexed keywords

BUS MATRIX SYNTHESIS; MACRO-MODELS; MULTI-PROCESSOR SYSTEM-ON-CHIPS (MPSOCS);

COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; POWER GENERATION;

COMMUNICATION SYSTEMS;

EID: 34547215354     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176254.1176327     Document Type: Conference Paper

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