Process variation aware bus-coding scheme for delay minimization in VLSI interconnects

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 43-46

  Raghunandan, C ^a   Sainarayanan, K S ^a   Srinivas, M B ^a  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS ENGINEERING; INTERCONNECTION NETWORKS;

CODING SCHEMES; DEEP SUB MICRON TECHNOLOGIES; DELAY MINIMIZATION; EFFECTIVE CAPACITANCE; ELECTRONIC DESIGNS; ENCODING SCHEMES; INTERCONNECT PERFORMANCE; INTERNATIONAL SYMPOSIUM; PROCESS PARAMETER VARIATIONS; PROCESS VARIABILITY; PROCESS VARIATIONS; VLSI INTERCONNECTS;

BUSES;

EID: 49749107072     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479695     Document Type: Conference Paper

References (13)

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