메뉴 건너뛰기




Volumn 2006, Issue , 2006, Pages 551-558

PowerViP: SoC power estimation framework at transaction level

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MATHEMATICAL MODELS; POWER SUPPLY CIRCUITS;

EID: 33748628807     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (56)

References (19)
  • 1
    • 0036625242 scopus 로고    scopus 로고
    • Cosimulation-based power estimation for system-on-chip design
    • M. Lajolo, A. Raghunathan, S. Dey, and L. Lavagno, "Cosimulation- based power estimation for system-on-chip design," IEEE Trans. on VLSI Systems, vol. 10, no. 3, pp. 253-266, 2002.
    • (2002) IEEE Trans. on VLSI Systems , vol.10 , Issue.3 , pp. 253-266
    • Lajolo, M.1    Raghunathan, A.2    Dey, S.3    Lavagno, L.4
  • 3
    • 27944476896 scopus 로고    scopus 로고
    • Power monitors: A framework for system-level power estimation using heterogeneous power models
    • N. Bansal, K. Lahiri, A. Raghunathan, and S. T. Chakradhar, "Power Monitors: a framework for system-level power estimation using heterogeneous power models," in Proc. Int. Conf. on VLSI Design, 2005, pp. 579-585.
    • (2005) Proc. Int. Conf. on VLSI Design , pp. 579-585
    • Bansal, N.1    Lahiri, K.2    Raghunathan, A.3    Chakradhar, S.T.4
  • 4
    • 0028722375 scopus 로고
    • Power analysis of embedded software: A first step towards software power minimization
    • V. Tiwari, S. Malik, and A. Wolfe, "Power analysis of embedded software: a first step towards software power minimization," IEEE Trans. on VLSI systems, vol. 2, no. 4, pp. 437-445, 1994.
    • (1994) IEEE Trans. on VLSI Systems , vol.2 , Issue.4 , pp. 437-445
    • Tiwari, V.1    Malik, S.2    Wolfe, A.3
  • 5
    • 0033719421 scopus 로고    scopus 로고
    • Wattch: A framework for architectural-level power analysis and optimizations
    • D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: a framework for architectural-level power analysis and optimizations," in Proc. ISCA, 2000, pp. 83-94.
    • (2000) Proc. ISCA , pp. 83-94
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 6
    • 0033712191 scopus 로고    scopus 로고
    • The design and use of SimplePower: A cycle-accurate energy estimation tool
    • W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "The design and use of SimplePower: a cycle-accurate energy estimation tool," in Proc. DAC, 2000, pp. 340-345.
    • (2000) Proc. DAC , pp. 340-345
    • Ye, W.1    Vijaykrishnan, N.2    Kandemir, M.3    Irwin, M.J.4
  • 8
    • 0034841273 scopus 로고    scopus 로고
    • JouleTrack: A web based tool for software energy profiling
    • A. Sinha and A. Chandrakasan, "JouleTrack: a web based tool for software energy profiling," in Proc. DAC, 2001, pp. 220-225.
    • (2001) Proc. DAC , pp. 220-225
    • Sinha, A.1    Chandrakasan, A.2
  • 10
    • 0036540701 scopus 로고    scopus 로고
    • Architectural power optimization by bus splitting
    • C.-T. Hsieh and M. Pedram, "Architectural power optimization by bus splitting," IEEE Trans. Computer Aided Design, vol. 21, no. 4, pp. 408-414, 2002.
    • (2002) IEEE Trans. Computer Aided Design , vol.21 , Issue.4 , pp. 408-414
    • Hsieh, C.-T.1    Pedram, M.2
  • 11
    • 0036625333 scopus 로고    scopus 로고
    • A bus energy model for deep submicron technology
    • P. P. Sotiriadis and A. P. Chandrakasan, "A bus energy model for deep submicron technology," IEEE Trans, on VLSI systems, vol. 10, no. 3, pp. 341-350, 2002.
    • (2002) IEEE Trans, on VLSI Systems , vol.10 , Issue.3 , pp. 341-350
    • Sotiriadis, P.P.1    Chandrakasan, A.P.2
  • 12
    • 0034258724 scopus 로고    scopus 로고
    • Architecture and synthesis algorithm for power-efficient bus interfaces
    • L. Benini, A. Macii, M. Poncino, and R. Scarsi, "Architecture and synthesis algorithm for power-efficient bus interfaces," IEEE Trans. Computer Aided Design, vol. 19, no. 9, pp. 969-980, 2000.
    • (2000) IEEE Trans. Computer Aided Design , vol.19 , Issue.9 , pp. 969-980
    • Benini, L.1    Macii, A.2    Poncino, M.3    Scarsi, R.4
  • 13
    • 84893740328 scopus 로고    scopus 로고
    • System-level power analysis methodology applied to the AMBA bus
    • M. Caldari et al., "System-level power analysis methodology applied to the AMBA bus," in Proc. DATE, 2003, pp. 32-37.
    • (2003) Proc. DATE , pp. 32-37
    • Caldari, M.1
  • 14
    • 3042520667 scopus 로고    scopus 로고
    • Energy estimation based on hierarchical bus models for power-aware smart card
    • U. Neffe et al., "Energy estimation based on hierarchical bus models for power-aware smart card," in Proc. DATE, 2004, pp. 300-305.
    • (2004) Proc. DATE , pp. 300-305
    • Neffe, U.1
  • 15
    • 3042613418 scopus 로고    scopus 로고
    • System level power modeling and simulation of high-end industrial network-on-chip
    • A. Bona, V. Zaccaria, and R. Zafalon, "System level power modeling and simulation of high-end industrial network-on-chip," in Proc. DATE, 2004, pp. 318-323.
    • (2004) Proc. DATE , pp. 318-323
    • Bona, A.1    Zaccaria, V.2    Zafalon, R.3
  • 16
    • 16244376510 scopus 로고    scopus 로고
    • Power analysis of system-level on-chip communication architectures
    • K. Lahiri and A. Raghunathan, "Power analysis of system-level on-chip communication architectures," in Proc. CODES+ISSS, 2004, pp. 236-241.
    • (2004) Proc. CODES+ISSS , pp. 236-241
    • Lahiri, K.1    Raghunathan, A.2
  • 19
    • 27544456315 scopus 로고    scopus 로고
    • Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling
    • R. Kumar, V. Zyuban, and D. Tullsen, "Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling", in Proc. ISCA, 2005, pp. 408-419.
    • (2005) Proc. ISCA , pp. 408-419
    • Kumar, R.1    Zyuban, V.2    Tullsen, D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.