Extending the transaction level modeling approach for fast communication architecture exploration

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 113-118

  Pasricha, Sudeep ^a   Dutt, Nikil ^a   Ben Romdhane, Mohamed ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Wireless Communications Division   (United States)

Author keywords

AMBA; Bus Cycle Accurate Modeling; Communication Architecture Exploration; Shared Bus Architectures; Transaction Level Modeling

Indexed keywords

ARCHITECTURAL DESIGN; BANDWIDTH; BENCHMARKING; COMMUNICATION SYSTEMS; COMPUTER SIMULATION; SWITCHING SYSTEMS; TIME DIVISION MULTIPLE ACCESS;

AMBA; ARCHITECTURE EXPLORATIONS; SHARED BUS ARCHITECTURES; TRANSACTION LEVEL MODELING BUS CYCLE ACCURATE MODELING;

SYSTEMS ANALYSIS;

EID: 4444364133     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996603     Document Type: Conference Paper

References (21)

1. D. Gajski et al., "SpecC: Specification Language and Methodology", Kluwer Academic Publishers, January 2000
2. Sudeep Pasricha, "Transaction Level Modeling of SoC with SystemC 2.0", Synopsys User Group Conference (SNUG), 2002
3. SystemC initiative, www.systemc.org
4. P. Paulin et al., "StepNP: A system-level exploration platform for network processors", IEEE Design and Test of Computers, 2002
5. Open Core Protocol International Partnership (OCP-IP), www.ocpip.org.
6. Cadence NCSystemC www.cadence.com/products/ncsystemc.html
7. Coware. www.coware.com
8. D. Flynn. "AMBA: enabling reusable on-chip designs". IEEE Micro, 17(4):20-27, July-Aug 1997
9. IBM CoreConnect www.chips.ibm.com/products/powerpc/cores
10. T. Grötker, S. Liao, G. Martin, S. Swan. "System Design with SystemC". Kluwer Academic Publishers, 2002
11. Xinping Zhu et al, "A hierarchical modeling framework for on-chip communication architectures", Proc. ICCAD, 2002
12. M. Caldari, M. Conti, M. Coppola, S. Curaba, L. Pieralisi, C. Turchetti "Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0", Proc. DATE 2003
13. O. Ogawa et al, "A Practical Approach for Bus Architecture Optimization at Transaction Level", Proc. DATE 2003
14. AHB CLI Specification www.arm.com/armtech/ahbcli
15. G. Nicolescu, et al, "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design", Proc. DATE, 2001
16. CoCentric Studio www.synopsys.com/products/cocentric_studio
17. J.A. Rowson and A. Sangiovanni-Vincentelli. "Interface-Based Design". Proc. DAC, 1997
18. AMBA AXI Specification www.arm.com/armtech/AXI
19. Reinaldo A. Bergamaschi and Salil Raje, "Observable Time Windows: Verifying the Results of High-Level Synthesis", Proc. European conference on Design and Test, 1996
20. K. Keutzer et al. "System-Level Design: Orthogonalization of Concerns and Platform-Based Design". IEEE Transactions on Computer-Aided Design. Vol. 19, No. 12. December 2000
21. Mohamed Ben-Romdhane et al. "Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis" Kluwer Academic Publishers, 1996