Analysis of delay variation in encoded on-chip bus signaling under process variation

Proceedings of the IEEE International Frequency Control Symposium and Exposition

Volumn , Issue , 2008, Pages 228-234

  Tuuna, Sampo ^a   Nigussie, Ethiopia ^a   Isoaho, Jouni ^a   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMOBILE DRIVERS; BANDPASS FILTERS; BREEDER REACTORS; BUSES; CAPACITANCE; DECODING; ELECTRIC LINES; POWER TRANSMISSION; TIME DELAY; TRANSMISSION LINE THEORY; WIRE;

45 NM TECHNOLOGY; DECOUPLING METHODS; DELAY VARIATIONS; DISTRIBUTED RLC; DUAL RAIL; EFFECTIVE CAPACITANCE; INTERNATIONAL CONFERENCES; LOAD CAPACITANCES; ON CHIP BUSES; ON-CHIP SIGNALING; PROCESS VARIATIONS; RISE TIME; TRANSMISSION LINE (TL); TRANSMISSION LINE MODEL (TLM); VLSI DESIGNS; VOLTAGE-MODE (VM);

MODAL ANALYSIS;

EID: 47649129937     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.2008.73     Document Type: Conference Paper

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