Power analysis of system-level on-chip communication architectures

Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004

Volumn , Issue , 2004, Pages 236-241

  Lahiri, Kanishka ^a   Raghunathan, Anand ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

Communication Architectures; Low Power Design; Network on Chip; Power Analysis; System on Chip

Indexed keywords

COMMUNICATION; DECODING; INTERFACES (COMPUTER); MULTIPLEXING; OPTIMIZATION; PROGRAM PROCESSORS;

COMMUNICATION ARCHITECTURE; LOW-POWER DESIGN; NETWORK-ON-CHIP; POWER ANALYSIS; SYSTEM-ON-CHIPS (SOC);

MICROPROCESSOR CHIPS;

EID: 16244376510     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016777     Document Type: Conference Paper

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