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Volumn 9, Issue 3, 2009, Pages 1015-1022

Novel top-down wafer-scale fabrication of single crystal silicon nanowires

Author keywords

[No Author keywords available]

Indexed keywords

CLEANROOM FACILITIES; DEVICE CHARACTERIZATIONS; DEVICE OPERATIONS; ELECTRICAL MEASUREMENTS; ELECTROCHEMICAL BEHAVIORS; FABRICATION TECHNOLOGIES; GENERAL DESCRIPTIONS; I-V CHARACTERISTICS; METAL LAYERS; METALLIC NANOWIRES; MICRO TECHNOLOGIES; MICRO-METER SCALE; OXIDIZED SILICONS; PROCESS TECHNOLOGIES; SENSOR APPLICATIONS; SINGLE CRYSTAL SILICONS; SITE BINDINGS; SPECIFIC CONTACT RESISTIVITIES; THIN-FILM DEPOSITIONS; TOP DOWNS; WAFER-SCALE; WAFER-SCALE FABRICATIONS;

EID: 65249093295     PISSN: 15306984     EISSN: None     Source Type: Journal    
DOI: 10.1021/nl803181x     Document Type: Article
Times cited : (91)

References (65)
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    • fo is the capacitance per unit area of the front-gate oxide.
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    • FG.
    • FG.
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    • Note: the realized silicon nanowires are wider than the metallic masking nanowires. Further optimization of the dry-etching transfer step will result in an improved transfer aspect ratio.
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    • fd(VFG, VFB, Na, Cfo, ξ(VFG, VFB, ξ2/4Cfo 2)1/2, κsε0/C fo, where ξ, 2κsε 0qNa)1/2
    • 1/2.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.