Timing variation-aware task scheduling and binding for MPSoC

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 137-142

  Chon, Haneul ^a   Kim, Taewhan ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE DESIGNS; CLOCK SPEED; CONVENTIONAL METHODS; DESIGN CONSTRAINTS; MULTIPROCESSOR SYSTEM ON CHIPS; RESOURCE-SHARING; STATIC TIMING ANALYSIS; SYSTEM LEVELS; SYSTEM-LEVEL DESIGNS; TASK-SCHEDULING; TIMING VARIATIONS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; MULTIPROCESSING SYSTEMS; MULTITASKING; SCHEDULING; SCHEDULING ALGORITHMS; SPACE RESEARCH; TIMING DEVICES;

TIME MEASUREMENT;

EID: 64549108475     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796470     Document Type: Conference Paper

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