Guaranteeing performance yield in high-level synthesis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 303-309

  Hung, W L ^a   Wu, Xiaoxia ^a   Xie, Yuan ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COMPUTER AIDED DESIGN; COMPUTER RESOURCE MANAGEMENT; DESIGN; MANAGEMENT; PLANNING; PROCESS ENGINEERING; PRODUCT DEVELOPMENT; RESOURCE ALLOCATION; SIMULATED ANNEALING; STATIC ANALYSIS; STATISTICAL METHODS; STATISTICS; TIME MEASUREMENT; TIMING CIRCUITS;

AREA REDUCTION; COMPUTER-AIDED DESIGN; DESIGN OBJECTIVES; DESIGN PARADIGMS; DESIGN-AUTOMATION TOOLS; DETERMINISTIC DESIGN; HIGH LEVEL SYNTHESIS (HLS); INTERNATIONAL CONFERENCES; PROBABILISTIC DESIGN; PROCESS VARIATIONS; SIMULATED ANNEALING ENGINE; SOLUTION SPACES; STATISTICAL STATIC TIMING ANALYSIS (SSTA); TASK SCHEDULING; TIMING CONSTRAINTS; TOTAL COMPLETION TIME;

PROCESS DESIGN;

EID: 46149112172     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320050     Document Type: Conference Paper

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