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Volumn , Issue , 2007, Pages 424-428

Timing variation-aware high-level synthesis

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DESIGN; ELECTRIC CURRENTS; TIME MEASUREMENT;

EID: 50249164346     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397302     Document Type: Conference Paper
Times cited : (32)

References (16)
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  • 4
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  • 5
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  • 6
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    • Statistical analysis of subthreshold leakage current for VLSI circuits
    • February
    • R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical analysis of subthreshold leakage current for VLSI circuits," IEEE TVLS, pp. 131-139, February 2004.
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  • 7
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    • Full-chip subthreshold leakage power prediction model for sub-0.1 μm CMOS
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  • 8
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    • Raj, S.1    Vrudhula, S.2    Wang, J.3
  • 9
    • 4444264520 scopus 로고    scopus 로고
    • Novel sizing algorithm for yield improvement under process variation in nanometer technology
    • S. Choi, B. C. Paul, and K. Roy, "Novel sizing algorithm for yield improvement under process variation in nanometer technology," In Proc. DAC, pp. 454-459, 2004.
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  • 10
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    • Statistical optimization of leakage power considering process variation using dual-Vth and sizing
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  • 11
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    • Variability inspired implementation selection problem
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  • 12
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  • 16
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.