Variation-aware task allocation and scheduling for MPSoC

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 598-603

  Wang, Feng ^a   Nicopoulos, C ^a   Wu, Xiaoxia ^a   Xie, Yuan ^a   Vijaykrishnan, N ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION METHODS; COMPUTER-AIDED DESIGN; DEEP SUB-MICRON DESIGNS; DELAY UNCERTAINTY; DESIGN HIERARCHY; INTERNATIONAL CONFERENCES; MULTI-PROCESSOR SYSTEM-ON-CHIP; NEW DESIGN; PARADIGM SHIFTS; PARAMETER VARIATIONS; PERFORMANCE CONSTRAINTS; PROCESS VARIATIONS; STATISTICAL DESIGNS; TASK ALLOCATION AND SCHEDULING; TASK SCHEDULING; YIELD IMPROVEMENTS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; GAS DYNAMIC LASERS; INTEGRATED CIRCUITS; SCHEDULING ALGORITHMS; STATISTICAL METHODS;

SCHEDULING;

EID: 50249182387     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397330     Document Type: Conference Paper

References (19)

1. Shekhar Borkar. Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro, 25(6):10-16, 2005.
2. A. Jerraya and W. Wolf. Multiprocessor systems-on-chips. Morgan Kaufmann Publishers, 2005.
3. G.C. Sih and E.A. Lee. A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures. IEEE Transactions on Parallel and Distributed Systems, 04(2):175-187, 1993.
4. W.H. Wolf. An architectural co-synthesis algorithm for distributed, embedded computing systems. IEEE Trans. Very Large Scale Integr. Syst., 5(2):218-229, 1997.
5. Y. Zhang, X. Hu, and D. Z. Chen. Task scheduling and voltage selection for energy minimization. In Design Automation Conference, pages 183-188, 2002.
6. L. Jiong and N. Jha. Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems. In 7th Asia and South Pacific Design Automation Conference, pages 719-726, 2002.
7. J. Hu and R. Marculescu. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. Design, Automation, and Test in Europe Conference, pages 234-239, 2004.
8. C. Hongliang and S. S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single pert-like traversal. In International Conference on Computer Aided Design, pages 621-625, 2003.
9. A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In International Conference on Computer Aided Design, pages 900-907, 2003.
10. D. Sinha, N. V. Shenoy, and H. Zhou. Statistical gate sizing for timing yield optimization. In IEEE/ACM International Conference on Computer-Aided Design, pages 1037-1041, 2005.
11. K. Chopra, S. Shah, A. Srivastava, D. Blaauw, and D. Sylvester. Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. International Conference on Computer-Aided Design, pages 1023-1028, November 2005.
12. K. A. Bowman, S. G. Duvall, and J. D. Meindl. Impact of Die-to-Die and Within Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration. Journal of Solid-State Circuits, pages 183-190, February 2002.
13. T. S. Tia, Z. Deng, M. Shankar, M. Storch, J. Sun, L. C. Wu, and J. W. S. Liu. Probabilistic performance guarantee for real-time tasks with varying computation times. In Real-Time Technology and Applications Symposium, pages 164-173, 1995.
14. X. S. Hu, Z. Tao, and E. H. M. Sha. Estimating probabilistic timing performance for real-time embedded systems. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 9(6):833-844, 2001. 1063-8210.
15. G. D. Veciana, M. F. Jacome, and J.-H. Guo. Hierarchical algorithms for assessing probabilistic constraints on system performance. In IEEE/ACM Design Automation Conference (DAC), pages 251-256, 1998.
16. C. Clark. The greatest of a finite set of random variables. Operations Research, pages 145-162, 1961.
17. Y. B. Li and J. Henkel. A framework for estimation and minimizing energy dissipation of embedded hw/sw systems. Design Automation Conference (DAC), pages 188-193, 1998.
18. R. Dick. Embedded systems synthesis benchmarks suite (e3s). http://www.ece.northwestern.edu/dickrp/e3s/.
19. Y. Xie and W. Hung. Temperature-aware task allocation and scheduling for embedded systems. Journal of VLSI Signal Processing, 45(3): pages 177-189, 2006.