Extraction, simulation and test generation for interconnect open defects based on enhanced aggressor-victim model

Proceedings - International Test Conference

Volumn , Issue , 2008, Pages

  Hillebrecht, Stefan ^a   Polian, Ilia ^a   Engelke, Piet ^a   Becker, Bernd ^a   Keim, Martin ^b   Cheng, Wu Tung ^b  

^a UNIVERSITY OF FREIBURG   (Germany)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

ATPG; Fault simulation; Interconnect opens; Open via defects

Indexed keywords

AGGRESSOR-VICTIM; ATPG; BIT PARALLELISM; DEFECT MODELING; EVENT-DRIVEN SIMULATIONS; FAULT SIMULATION; HIGH EFFICIENCY; INTERCONNECT OPENS; NEW CLASS; NOISE MARGINS; OPEN-VIA DEFECTS; ORDERS OF MAGNITUDE; STUCK-AT FAULTS; TEST GENERATION COMPLEXITY; TEST GENERATIONS; TEST PATTERN; UNTESTABLE FAULTS;

TESTING;

DEFECTS;

EID: 67249161649     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2008.4700642     Document Type: Conference Paper

References (18)

1. B. Koenemann. Test in the era of "What you see is NOT what you get". In Int'l Test Conf., page 12, 2004. (Keynote address).
2. S.P. Murarka, I.V. Verner, and R.J. Gutmann. Copper-Fundamental Mechanisms for Microelectronis Applications. John Wiley & Sons, 2000.
3. R. Blish, T. Dellin, S. Huther, M. Johnson, J. Maiz, B. Likins, N. Lycoudes, J. McPherson, Y. Peng, C. Peridier, A. Preussger, G. Propkop, and L. Tullos. Critical Reliability Challenges for the International Technology Roadmap for Semiconductors (ITRS), 2003.
4. V.H. Champac, R. Rodriguez-Montanes, J .A. Segura, J. Figueras, and J.A. Rubio. Fault modelling of gate oxide short, floating gate and bridging failures in CMOS circuits. In European Test Conf., pages 143-148, 1991.
5. M. Renovell and G. Cambon. Electrical analysis and modeling of floating-gate fault. IEEE Trans. on CAD, 11(11):1450-1458, 1992.
6. S. Rafiq, A. Ivanov, S. Tabatabaei, and M. Renovell. Testing for floating gates defects in CMOS circuits. In Asian Test Symp., pages 228- 236, 1998.
7. D. Aruḿi, Rodŕiguez-Montańes, and J. Figueras. Experimental characterization of CMOS interconnect open defects. IEEE Trans. on CAD, 27(1):123-136, 2008.
8. R. Gómez, A. Girón, and V. Champac. Test of interconnection opens considering coupling signals. In IEEE Defect and Fault Tolerance Symp., pages 247-255, 2005.
9. S. Spinner, I. Polian, P. Engelke, B. Becker, M. Keim, and W.-T. Cheng. Automatic test pattern generation for interconnect open defects. In VLSI Test Symp., pages 181-186, 2008.
10. Y. Sato, I. Yamazaki, H. Yamanaka, T. Ikeda, and M. Takakura. A persistent diagnostic technique for unstable defects. In Int'l Test Conf., pages 242-249, 2002.
11. H. Konuk and F. Joel Ferguson. Oscillation and sequential behavior caused by interconnect opens in digital CMOS circuits. In Int'l Test Conf., pages 597-606, 1997.
12. S. Spinner, J. Jiang, I. Polian, P. Engelke, and B. Becker. Simulating open-via defects. In Asian Test Symp., pages 265-270, 2007.
13. I. Polian, P. Engelke, M. Renovell, and B. Becker. Modeling feedback bridging faults with non-zero resistance. Jour. of Electronic Testing: Theory and Applications, 21(1):57-69, 2005.
14. I. Hamzaoglu and J. Patel. Test set compaction algorithms for combinational circuits. IEEE Trans. on CAD, 19(8):957-963, 2000.
15. E.M. Rudnick and J. Patel. Efficient techniques for dynamic test sequence compaction. IEEE Trans. on Computers, 48(3):323-330, 1999.
16. W. Moore, G. Gronthoud, K. Baker, and M. Lousberg. Delay-fault testing and defects in deep sub-micron - does critical resistance really mean anything. In Int'l Test Conf., pages 95-104, 2000.
17. A. Czutro, N. Houarche, P. Engelke, I. Polian, M. Comte, M. Renovell, and B. Becker. A simulator of small-delay faults caused by resistive-open defects. In European Test Symp., pages 113-118, 2008.
18. B.R. Benware, R. Madge, C. Lu, and R. Daasch. Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs. In VLSI Test Symp., pages 39-46, 2003.