Detailed placement for enhanced control of resist and etch CDs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 12, 2007, Pages 2144-2157

  Gupta, Puneet ^a,b   Kahng, Andrew B ^a,c   Park, Chul Hong ^a,d  

^a IEEE

^b Blaze DfM   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Defocus; Etch; Lithography; Placement; SRAF

Indexed keywords

DEFOCUS; ETCH PROCESSES;

DYNAMIC PROGRAMMING; FEATURE EXTRACTION; LITHOGRAPHY; OPTIMIZATION; PROGRAM PROCESSORS;

COMPACT DISKS;

EID: 36348987328     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.906998     Document Type: Article

References (22)

1. KLA-Tencor ProLith User's Manual.
2. International Technology Roadmap for Semiconductors, 2005, http://public.itrs.net
3. L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, "Toward a Methodology for Manufacturability Driven Design Rule Exploration", Proc.ACM/IEEE DAC, June 2004, pp. 311-316.
4. Yuri Granik, "Correction for etch proximity: new models and applications," Proc. SPIE, vol. 4346, 2001, pp. 98-112
5. A. B. Kahng and S. Mantik, "Measurement of Inherent Noise in EDA Tools", Proc. ISQED , 2002, pp. 206-211.
6. P. Gupta and A. B. Kahng, "Manufacturing-Aware Physical Design", Proc. IEEE/ACM ICCAD, Nov. 2003, pp. 681-687.
7. P. Gupta, A. B. Kahng and C.-H. Park, "Detailed Placement for Improved Depth of Focus and CD Control", Proc. Asia and South Pacific Design Automation Conf., Jan. 2005, pp. 343-348.
8. P. Gupta, A. B. Kahng and C.-H. Park, "Manufacturing-aware Design Methodology for Assist Feature Correctness", Proc. SPIE , Feb. 2005, pp. 131-140.
9. P. Gupta, A. B. Kahng and C.-H. Park,"Enhanced resist and etch CD control by design perturbation", Proc. 25th BACUS Symposium on Photomask Technology and Management, Nov. 2005, Vol. 5992, pp. 59923P-1-59923P-11.
10. K. Hashimoto, T. Kuji, Sh. Tokutome, T. Kotani, S. Tanaka and S. Inoue, "A Tandem Process Proximity Correction Method," Proc. SPIE, vol. 4691, 2002, pp. 1070-1081.
11. K. Kim, Y. Choi, R. Socha and D. Flagello, "Optimization of Process Condition to Balance MEF and OPC for Alternating PSM," Proc. SPIE, Vol. 4691, 2002, pp. 240-246.
12. L.W. Liebmann, "Layout Impact of Resolution Enhancement Techniques: Impediment or Opportunity?", Proc. IEEE/ACM ISPD, 2003, pp. 110-117.
13. M. Levenson, N. Viswanathan and R. Sympson, "Improving resolution in photolithography with a phase-shifting mask," IEEE Trans. Electron. Dev., vol. 29, pp. 1812-1846, Dec. 1982.
14. C.-H. Park, Y-H. Kim, J.-S. Park, K. Kim, M.-H. Yoo and J.-T. Kong, "A Systematic Approach to Correct Critical Patterns Induced by the Lithography Process at the Full-chip Level," Proc. SPIE, vol. 3679, 1999, pp. 622-700.
15. J. Petersen, "Analytical Description of Anti-scattering and Scattering Bar Assist Features," Proc. SPIE, Vol. 4000, 2000, pp. 77-89.
16. F.M. Schellenberg, L. Capodieci and R. Socha, "Adoption of OPC and the Impact on Design and Layout", Proc. IEEE/ACM DAC, 2001, pp. 89-92.
17. X. Shi, S. Hsu, F. Chen, M. Hsu, R. Socha and M. Dusa, "Understanding the Forbidden Pitch Phenomenon and Assist Feature Placement", Proc. SPIE, Vol. 4689, 2002, pp. 985-996.
18. R. Socha, M. Dusa, L. Capodieci, J. Finders, F. Chen, D. Flagello and K. Cummings, "Forbidden Pitches for 130nm Lithography and Below." Proc. SPIE, Vol. 4000, 2000, pp. 1140-1155.
19. J. Stirniman and M. Rieger, "Fast proximity correction with zone sampling," Proc. SPIE, vol. 2197, 1994, pp. 294-301.
20. A. Wong, R. Ferguson, S. Mansfield, A. Molless, D. Samuels, R. Schuster and A. Thomas, "Level-Specific Lithography Optimization for 1-Gb DRAM," IEEE Trans. on Semiconductor Manufacturing, 13(1), 2000, pp. 76-87.
21. J. Word, S. Zhu and J. Sturtevant, "Assist Feature OPC Implementation for the 130nm Technology Node with KrF and No Forbidden Pitches," Proc. SPIE, Vol. 4691, 2002, pp. 1139-1147.
22. A. B. Kahng, I. Markov and S. Reda, "On Legalization of Row-Based Placements" Proc. IEEE Great Lakes VLSI Symposium, 2004, pp. 214-219.