Strained Si/SiGe MOS technology: Improving gate dielectric integrity

Microelectronic Engineering

Volumn 86, Issue 3, 2009, Pages 218-223

  Olsen, S H ^a   Yan, L ^a   Agaiby, R ^a   Escobedo Cousin, E ^a   O'Neill, A G ^a   Hellstrom P E ^b   Ostling M ^b   Lyutovich, K ^c   Kasper, E ^c   Claeys, C ^d   Parker, E H C ^e  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^c UNIVERSITY OF STUTTGART   (Germany)

^d IMEC   (Belgium)

^e UNIVERSITY OF WARWICK   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY; FIELD EFFECT TRANSISTORS; GATE DIELECTRICS; GATES (TRANSISTOR); HEATING; INTEGRATED CIRCUIT LAYOUT; MODELS; MOS CAPACITORS; MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SURFACE ROUGHNESS;

DIELECTRIC INTEGRITIES; DOMINATING FACTORS; EXPERIMENTAL DATUM; GATE LEAKAGES; GATE OXIDE INTEGRITIES; LOW THERMAL CONDUCTIVITIES; MISFIT DISLOCATIONS; MOS TECHNOLOGIES; MOSFET CHANNELS; MOSFETS; PERFORMANCE GAINS; PHYSICAL MODELS; SELF-HEATING; SELF-HEATING EFFECTS; SHORT CHANNELS; SI/SIGE; STRAIN-RELIEVING; STRAINED-SI; STRAINED-SI/SIGE; VIRTUAL SUBSTRATES;

SUBSTRATES;

EID: 59049086315     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2008.08.001     Document Type: Article

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