Comparison of network-on-chip mapping algorithms targeting low energy consumption

IET Computers and Digital Techniques

Volumn 2, Issue 6, 2008, Pages 471-482

  Marcon, C A M ^a   Moreno, E I ^a   Calazans, N L V ^a   Moraes, F G ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANNEALING; BIOLOGICAL MATERIALS; CONFORMAL MAPPING; ELECTRIC LOAD FORECASTING; ELECTRIC NETWORK TOPOLOGY; HEURISTIC ALGORITHMS; LASER FUSION; NETWORK PROTOCOLS; SENSOR NETWORKS; SIMULATED ANNEALING; STOCHASTIC PROGRAMMING; TABU SEARCH;

APPLICATIONS.; ENERGY SAVINGS; EXECUTION TIMES; EXHAUSTIVE SEARCHES; HEURISTIC; HEURISTIC APPROACHES; HEURISTICS; INCREMENTAL; LOW ENERGIES; LOW ENERGY CONSUMPTIONS; MAPPING ALGORITHMS; MAPPING PROBLEMS; NETWORK-ON-CHIP; SOC DESIGNS; STOCHASTIC ALGORITHMS; STOCHASTIC SEARCH METHODS; WEIGHTED MODELS;

HEURISTIC METHODS;

EID: 54949125707     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt:20070111     Document Type: Article

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