OptiMap: A tool for automated generation of NoC architectures using multi-port routers for FPGAs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Sethuraman, Balasubramanian ^a   Vemuri, Ranga ^a  

^a University of Cincinnati   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUSBARS; COMPUTER ARCHITECTURE; CONFORMAL MAPPING; CONSTRAINT THEORY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); ROUTERS; SYSTEMS ANALYSIS;

MULTIPLE LOGIC CORES; MULTIPORT ROUTERS; NETWORKS ON CHIP (NOC); TASK GRAPH;

MICROPROCESSOR CHIPS;

EID: 34047120251     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243837     Document Type: Conference Paper

References (15)

1. Balasubramanian Sethuraman et al. LiPaR: A Light-Weight Parallel Router for FPGA-based Networks-on-Chip. In 15th Great Lakes Symposium on VLSI (GLSVLSI'05), 2005.
2. C.A. Zerferino et al. ParlS: A Parametric and Scalable Network on Chip. In SBCCI'2004, 2004.
3. W. Daily and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In DAC, 2001.
4. D.Bertozzi et al. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. Parallel and Distributed Systems, IEEE Trans. on, 16(2):113-129, 2005.
5. Fernando Moraes et al. A Low Area Overhead Packet-switched Network On Chip: Architecture and Prototyping. In IFIP VLSI-SOC 2003, pages 318-323, 2003.
6. J. Hu and R. Marculesu. Exploiting the routing flexibility for energy/performance aware mapping of regular noc architectures. In DATE'03, pages 688-693, 2003.
7. International Sematech. International Technology Roadmap for Semiconductors. In http://public.itrs.net, 2002.
8. N. Kavaldjiev and G. J. Smit. A survey of efficient on-chip communications for SoC. In PROGRESS 2003 Embedded Systems Symposium, October 2003.
9. Y.-K. Kwok and I. Ahmad. Dynamic critical-path scheduling: An effective technique for allocating task graphs to multiprocessors. Parallel Distributed Systems, IEEE Transactions on, 7(5):506-52l, 1996.
10. L. Benini and G. De Micheli. Networks on Chips: A New SOC Paradigm. In IEEE Computer, pages 70-78, Jan 2002.
11. T. Lei and S. Kumar. A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In Euromicro Symposium on Digital System Design, 2003.
12. MentorGraphics Inc. http://www.mentorgraphics.com.
13. R.P. Dick et al. TGFF: Task Graphs For Free. In 6th International Workshop on Hardware/Software Codesign, 1998.
14. Shashi Kumar et al. A Network on Chip Architecture and Design Methodology. In Annual Symposium on VLSI'2002, IEEE CS Press, pages 105-112, 2002.
15. Xilinx Inc. http://www.xilinx.com, 2004.