Address generation optimization for embedded high-performance processors: A survey

Journal of Signal Processing Systems

Volumn 53, Issue 3, 2008, Pages 271-284

  Talavera, Guillermo ^a   Jayapala, Murali ^b   Carrabina, Jordi ^a   Catthoor, Francky ^b  

^a UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

^b IMEC   (Belgium)

Author keywords

Address generation; Embedded; Optimization

Indexed keywords

ADDRESS GENERATION; ADDRESS GENERATORS; COMPUTATIONAL PERFORMANCE; COMPUTATIONAL RESOURCES; COMPUTING ELEMENTS; DATA PARALLELISMS; DATA PATHS; DISTRIBUTED MEMORIES; EMBEDDED; EMBEDDED ARCHITECTURES; EMBEDDED PROCESSORS; GENERAL-PURPOSE PROCESSORS; GENERATOR UNITS; GLOBAL TRADING; HIGH-PERFORMANCE PROCESSORS; LOW POWERS; MEMORY BANDWIDTHS; NUMBER OF DATA; PARALLEL COMPUTATIONS; PROGRAMMABILITY; REASONABLE ENERGY; RESEARCH TRENDS; RUNNING-IN; SPEED UPS; TIME-TO-MARKET; VERY LONG INSTRUCTION WORDS;

ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; CONCURRENT ENGINEERING; DATA STORAGE EQUIPMENT; INTEGRATED CIRCUITS; OPTIMIZATION; PROGRAM COMPILERS; RATE CONSTANTS; SURVEYS; TELECOMMUNICATION SYSTEMS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EMBEDDED SYSTEMS;

EID: 53649099340     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-008-0165-y     Document Type: Article

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