A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 5, 2003, Pages 689-695

  Mathew, Sanu ^a   Anders, Mark ^a   Krishnamurthy, Ram K ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Address generation unit (AGU); High performance adders; Semidynamic design; Sparse tree adder

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; PERFORMANCE; THRESHOLD VOLTAGE;

ADDRESS GENERATION UNIT; SEMIDYNAMIC DESIGN; SPARSE-TREE ADDER;

MICROPROCESSOR CHIPS;

EID: 0037515315     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.810056     Document Type: Article

References (12)

1. IA-32 Intel® Architecture Software Developer's Manual, vol. 1, Intel Corp., Hillsboro, OR, pp. 1-22.
2. D. Harris and S. Naffziger, "Statistical clock skew modeling with data delay variations," IEEE Trans. VLSI Syst., vol. 9, pp. 888-898, Dec 2001.
3. D. S. Sager et al., "A 0.18 μm CMOS IA32 microprocessor with a 4 GHz integer execution unit," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, pp. 324-325.
4. t transistors and 6 layers of Cu interconnects," in IEDM Tech. Dig., Dec. 2000, pp. 567-570.
5. P. Kogge and H. S. Stone, "A parallel algorithm for the efficient solution of a general class of recurrence equations," IEEE Trans. Comput., vol. C-22, pp. 786-793, Aug 1973.
6. J. Park, H. Ngo, J. Silberman, and S. Dhong, "470-ps 64-bit parallel binary adder," in Dig. Tech. Papers, Int. Symp. VLSI Circuits, Systems, and Applications, 2000, pp. 192-193.
7. S. Mathew, M. Anders, R. Krishnamurthy, and S. Borkar, "A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core," Dig. Tech. Papers, Int. Symp. VLSI Circuits, Systems, and Applications, pp. 126-127, June 2002.
8. S. Mathew, R. Krishnamurthy, M. Anders, R. Rios, K. Mistry, and K. Soumyanath, "Sub-500 ps 64-b ALUs in 0.18 mm SOI/bulk CMOS: Design and scaling trends," IEEE J. Solid-State Circuits, vol. 36, pp. 1636-1646, Nov. 01.
9. S. Knowles, "A family of adders," in Proc. 14th IEEE Symp. Computer Arithmetic, Apr. 1999, pp. 277-281.
10. S. Naffziger, "A sub-nanosecond 0.5 μm 64 b adder design," IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 362-363, 1996.
11. J. Davis, "Interconnect limits on gigascale integration (GSI) in the 21st century," Proc. IEEE, vol. 89, pp. 305-324, Mar. 2001.
12. T. Ghani et al., "Scaling challenges and device design requirements for high performance sub-50-nm gate length planar CMOS transistors," in Dig. Tech. Papers, Int. Symp. VLSI Circuits, Systems, and Applications, June 2000, pp. 174-175.