Code generation for embedded processors

Proceedings of the International Symposium on System Synthesis

Volumn 2000-January, Issue , 2000, Pages 173-178

  Leupers, R ^a  

^a TU DORTMUND UNIVERSITY   (Germany)

Author keywords

Application specific processors; Computer science; Digital signal processing; Embedded system; Hardware; Microcontrollers; Program processors; Reduced instruction set computing; Registers; Time factors

Indexed keywords

APPLICATION PROGRAMS; C (PROGRAMMING LANGUAGE); CODES (SYMBOLS); COMPUTER HARDWARE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SCIENCE; COMPUTER SOFTWARE PORTABILITY; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; HIGH LEVEL LANGUAGES; INDUSTRIAL RESEARCH; MICROCONTROLLERS; MICROPROCESSOR CHIPS; NETWORK COMPONENTS; PROGRAM PROCESSORS; REAL TIME SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; SIGNAL PROCESSING; SYNTHESIS (CHEMICAL);

APPLICATION SPECIFIC PROCESSORS; ARCHITECTURAL FEATURES; COMPILER TECHNOLOGY; MULTIMEDIA PROCESSORS; PROGRAMMABLE PROCESSORS; REAL TIME CONSTRAINTS; REGISTERS; TIME FACTORS;

PROGRAM COMPILERS;

EID: 35248854748     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSS.2000.874046     Document Type: Conference Paper

References (77)

1. G. Arnout: SystemC Standard, Asia South Pacific Design Automation Conference (ASP-DAC), 2000
2. D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, S. Zhao: SpecC: Specification Language and Methodology, Kluwer Academic Publishers, 2000
3. J.L. Hennessy, D.A. Patterson: Computer Architecture - A Quantitative Approach, Morgan Kaufmann Publishers Inc., 1990
4. ARM home page: www.arm.com, 2000
5. Texas Instruments: www.ti.com/sc/c6x, 2000
6. Philips Semiconductors: www.trimedia.philips.com, 2000
7. Tensilica Inc.: www.tensilica.com, 2000
8. Austria Mikro Systeme International: www.amsint.com/databooks/digital/gepard.html, 2000
9. V. Zivojnovic, J.M. Velarde, C. Schläger, H. Meyr: DSPStone - A DSP-oriented Benchmarking Methodology, Int. Conf. on Signal Processing Applications and Technology (ICSPAT), 1994
10. P. Paulin, M. Cornero, C. Liem, et al.: Trends in Embedded Systems Technology, in: M.G. Sami, G. De Micheli (eds.): Hardware/Software Codesign, Kluwer Academic Publishers, 1996
11. M. Levy: C Compilers for DSPs flex their Muscles, EDN Access, Issue 12, www.ednmag.com, 1997
12. M. Coors, O. Wahlen, H. Keding, O. Lüthje, H. Meyr: TI C62x Performance Code Optimization, DSP Germany, 2000
13. A.V. Aho, R. Sethi, J.D. Ullman: Compilers - Principles, Techniques, and Tools, Addison-Wesley, 1986
14. S.S. Muchnik: Advanced Compiler Design & Implementation, Morgan Kaufmann Publishers, 1997
15. A.W. Appel: Modern Compiler Implementation in C, Cambridge University Press, 1998
16. S. Gupta, R. Gupta, M. Miranda, F. Catthoor: Analysis of High-Level Address Code Transformations for Programmable Processors, Design Automation & Test in Europe (DATE), 2000
17. R. Leupers, P. Marwedel: Function Inlining under Code Size Constraints for Embedded Processors, Int. Conference on Computer-Aided Design (ICCAD), 1999
18. M. Lam: Software Pipelining: An Effective Scheduling Technique for VLIW machines, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1988
19. G. Goossens, J. Vandewalle, H. De Man: Loop Optimization in Register-Transfer Scheduling for DSP Systems, 26th Design Automation Conference (DAC), 1989
20. U. Banerjee: Loop Transformations for Restructuring Compilers - The Foundations, Kluwer Academic Publishers, 1993
21. A.V. Aho, M. Ganapathi, S.W.K Tjiang: Code Generation Using Tree Matching and Dynamic Programming, ACM Trans. on Programming Languages and Systems 11, No. 4, 1989
22. C.W. Fraser, D.R. Hanson, T.A. Proebsting: Engineering a Simple, Efficient Code GeneratorGenerator, ACM Letters on Programming Languages and Systems, vol. 1, no. 3, 1992
23. H. Emmelmann, F.W. Schröer, R. Landwehr: BEG - A Generator for Efficient Backends, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), SIGPLAN Notices 24, no. 7, 1989
24. K. Rimey, P.N. Hilfinger: Lazy Data Routing and Greedy Scheduling for Application-Specific Signal Processors, 21st Annual Workshop on Microprogramming and Microarchitecture (MICRO-21), 1988
25. R. Hartmann: Combined Scheduling and Data Routing for Programmable ASIC Systems, European Conference on Design Automation (EDAC), 1992
26. B. Wess: Automatic Code Generation for Integrated Digital Signal Processors, IEEE Int. Symp. on Circuits and Systems (ISCAS), 1991
27. G. Araujo, S. Malik: Optimal Code Generation for Embedded Memory Non-Homogeneous Register Architectures, 8th Int. Symp. on System Synthesis (ISSS), 1995
28. G. Araujo, S. Malik, M. Lee: Using Register Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures, 33rd Design Automation Conference (DAC), 1996
29. R. Leupers: Register Allocation for Common Subexpressions in DSP Data Paths, Asia South Pacific Design Automation Conference (ASP-DAC), 2000
30. S. Novack, A. Nicolau, N. Dutt: A Unified Code Generation Approach using Mutation Scheduling, chapter 12 in [76]
31. S. Hanono, S. Devadas: Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator, 35th Design Automation Conference (DAC), 1998
32. B. Rau, V. Kathail, S. Aditya: Machine Description Driven Compilers for EPIC and VLIW Processors, Design Automation for Embedded Systems, Vol. 4, No. 2/3, Kluwer Academic Publishers, 1999
33. S. Bashford, R. Leupers: Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths, Design Automation for Embedded Systems, Vol. 4, No. 2/3, Kluwer Academic Publishers, 1999
34. M. Mahmood, F. Mavaddat, M.I. Elmasry: Experiments with an Efficient Heuristic Algorithm for Local Microcode Generation, Int. Conf. on Computer Design (ICCD), 1990
35. M. Langevin, E. Cerny: An Automata-Theoretic Approach to Local Microcode Generation, European Conference on Design Automation (EDAC), 1993
36. T. Wilson, G. Grewal, B. Halley, D. Banerji: An Integrated Approach to Retargetable Code Generation, 7th Int. Symp. on High-Level Synthesis (HLSS), 1994
37. R.J. Fisher, H.G. Dietz: Compiling for SIMD Within a Register, 11th Annual Workshop on Languages and Compilers for Parallel Computing (LCPC98), 1998
38. Intel: Coding Techniques for the Streaming SIMD Extensions With the Intel C/C++ Compiler, developer.intel.com/vtune/newsletr/methods.htm, 2000
39. R. Leupers: Code Selection for Media Processors with SIMD Instructions, Design Automation & Test in Europe (DATE), 2000
40. D.B. Powell, E.A. Lee, W.C. Newman: Direct Synthesis of Optimized DSP Assembly Code from Signal Flow Block Diagrams, Proc. International Conference on Acoustics, Speech, and Signal Processing, 1992
41. A. Sudarsanam, S. Malik: Memory Bank and Register Allocation in Software Synthesis for ASIPs, Int. Conf. on Computer-Aided Design (ICCAD), 1995
42. M. Saghir, P. Chow, C. Lee: Exploiting Dual Data-Memory Banks in Digital Signal Processors, 7th International Conference on Architectural Support for Programming Languages and Operating Systems, 1996
43. P. Grun, N. Dutt, A. Nicolau: Memory Aware Compilation through Accurate Timing Extraction, 37th Design Automation Conference (DAC), 2000
44. D.H. Bartley: Optimizing Stack Frame Accesses for Processors with Restricted Addressing Modes, Software - Practice and Experience, vol. 22(2), 1992
45. S. Liao, S. Devadas, K. Keutzer, S. Tjiang, A. Wang: Storage Assignment to Decrease Code Size, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1995
46. R. Leupers, P. Marwedel: Algorithms for Address Assignment in DSP Code Generation, Int. Conference on Computer-Aided Design (ICCAD), 1996
47. A. Sudarsanam, S. Liao, S. Devadas: Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures, Design Automation Conference (DAC), 1997
48. B. Wess, M. Gotschlich: Optimal DSP Memory Layout Generation as a Quadratic Assignment Problem, Int. Symp. on Circuits and Systems (ISCAS), 1997
49. B. Wess, M. Gotschlich: Constructing Memory Layouts for Address Generation Units Supporting Offset 2 Access, Proc. ICASSP, 1997
50. N. Kogure, N. Sugino, A. Nishihara: Memory Address Allocation Method for a DSP with ± 2 Update Operations in Indirect Addressing, European Conference on Circuit Theory and Design (ECCTD), 1997
51. R. Leupers, F. David: A Uniform Optimization Technique for Offset Assignment Problems, 11th Int. System Synthesis Symposium (ISSS), 1998
52. A. Rao, S. Pande: Storage Assignment using Expression Tree Transformations to Generate Compact and Efficient DSP Code, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1999
53. S. Davidson, D. Landskov, B.D. Shriver, P.W. Mallett: Some Experiments in Local Microcode Compaction for Horizontal Machines, IEEE Trans. on Computers, Vol. 30, No. 7, 1981
54. R. Leupers, P. Marwedel: Time-Constrained Code Compaction for DSPs, 8th Int. System Synthesis Symposium (ISSS), 1995
55. A. Timmer, M. Strik, J. van Meerbergen, J. Jess: Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores, 32nd Design Automation Conference (DAC), 1995
56. J.A. Fisher: Trace Scheduling: A Technique for Global Microcode Compaction, IEEE Trans. on Computers, vol. 30, no. 7, 1981
57. A. Aiken, A. Nicolau: A Development Environment for Horizontal Microcode, IEEE Trans. on Software Engineering, no. 14, 1988
58. B. Mesman, C. Alba Pinto, K. van Eijk: Efficient Scheduling of DSP Code on Processors with Distributed Register Files, 12th Int. Symp. on System Synthesis (ISSS), 1999
59. Edison Design Group: www.edg.com, 2000
60. Trimaran - An Infrastructure for Research in Instruction-Level Parallelism, www.trimaran.org, 2000
61. The Stanford Compiler Group: suif.stanford.edu, 2000
62. Machine SUIF: www.eecs.harvard.edu/hube/research/machsuif.html, 2000
63. Free Software Foundation: www.gnu.org, 1999
64. LANCE C compiler system: ls12-www.cs.uni-dortmund.de/~leupers, 2000
65. M. Lee, V. Tiwari, S. Malik, M. Fujita: Power Analysis and Minimization Techniques for Embedded DSP Software, IEEE Trans. on VLSI Systems, Vol. 5, No. 2, 1997
66. C. Gebotys: Low Energy Memory and Register Allocation Using Network Flow, 34th Design Automation Conference (DAC), 1997
67. P. Marwedel: Tree-based Mapping of Algorithms to Predefined Structures, Int. Conf. on Computer-Aided Design (ICCAD), 1993
68. R. Leupers, P. Marwedel: Retargetable Generation of Code Selectors from HDL Processor Models, European Design & Test Conference (ED & TC), 1997
69. D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, G. Goossens: CHESS: Retargetable Code Generation for Embedded DSP Processors, chapter 5 in [76]
70. C. Liem: Retargetable Compilers for Embedded Core Processors, Kluwer Academic Publishers, 1997
71. N. Dutt, P. Grun, A. Halambi: www.cecs.uci.edu/~aces, Center for Embedded Computer Systems, UC Irvine, 2000
72. ACE Associated Compiler Experts: www.ace.nl, 2000
73. Target Compiler Technologies: www.retarget.com, 2000
74. Archelon Inc.: www.archelon.com, 2000
75. P. Faraboschi, G. Desoli, J.A. Fisher: VLIW Architectures for DSP and Multimedia Applications - The Latest Word in Digital and Media Processing, IEEE Signal Processing Magazine, March 1998
76. P. Marwedel, G. Goossens (eds.): Code Generation for Embedded Processors, Kluwer Academic Publishers, 1995
77. R. Leupers: Retargetable Code Generation for Digital Signal Processors, Kluwer Academic Publishers, 1997