-
2
-
-
0026388570
-
A new address generation unit architecture for video signal processing
-
K. Kitagaki, T. Oto, T. Demura, Y. Araki, and T. Takada, "A new address generation unit architecture for video signal processing," Visual Commun., Image Processing'91: Image Processing, vol. 1606, pp. 891-900, 1991.
-
(1991)
Visual Commun., Image Processing'91: Image Processing
, vol.1606
, pp. 891-900
-
-
Kitagaki, K.1
Oto, T.2
Demura, T.3
Araki, Y.4
Takada, T.5
-
3
-
-
0029697471
-
Address calculation for retargetable compilation and exploration of instruction-set architectures
-
C. Liem, P. Paulin, and A. Jerraya, "Address calculation for retargetable compilation and exploration of instruction-set architectures," in Proc. 33rd ACM Design Automation Conf., 1996, pp. 597-600.
-
(1996)
Proc. 33rd ACM Design Automation Conf.
, pp. 597-600
-
-
Liem, C.1
Paulin, P.2
Jerraya, A.3
-
5
-
-
0030679984
-
Analysis and evaluation of address arithmetic capabilities in custom DSP architectures
-
A. Sudarsanam, S. Liao, and S. Devadas, "Analysis and evaluation of address arithmetic capabilities in custom DSP architectures," in Proc. 34th ACM Design Automation Conf., 1997, pp. 287-292.
-
(1997)
Proc. 34th ACM Design Automation Conf.
, pp. 287-292
-
-
Sudarsanam, A.1
Liao, S.2
Devadas, S.3
-
6
-
-
0029700806
-
Power exploration for data dominated video applications
-
S. Wuytack, F. Catthoor, L. Nachtergaele, and H. De Man, "Power exploration for data dominated video applications," in Proc. IEEE Int. Symp. on Low Power Design, 1996, pp. 359-364.
-
(1996)
Proc. IEEE Int. Symp. on Low Power Design
, pp. 359-364
-
-
Wuytack, S.1
Catthoor, F.2
Nachtergaele, L.3
De Man, H.4
-
7
-
-
0027042648
-
Phideo: A silicon compiler for high speed algorithms
-
P. Lippens, J. Van Meerbergen, A. Van der Werf, W. Verhaegh, B. McSweeney, J. Huisken, and O. McArdle, "Phideo: A silicon compiler for high speed algorithms," in Proc. 2nd ACM/IEEE European Conf. for Design Automation, 1991, pp. 436-441.
-
(1991)
Proc. 2nd ACM/IEEE European Conf. for Design Automation
, pp. 436-441
-
-
Lippens, P.1
Van Meerbergen, J.2
Van Der Werf, A.3
Verhaegh, W.4
McSweeney, B.5
Huisken, J.6
McArdle, O.7
-
9
-
-
0027961755
-
Optimization of address generator hardware
-
D. Grant, J. Van Meerbergen, and P. Lippens, "Optimization of address generator hardware," in Proc. 5th ACM/IEEE European Design and Test Conf., 1994, pp. 325-329.
-
(1994)
Proc. 5th ACM/IEEE European Design and Test Conf.
, pp. 325-329
-
-
Grant, D.1
Van Meerbergen, J.2
Lippens, P.3
-
11
-
-
0028758429
-
Address equation multiplexing for real time signal processing applications
-
J. Rabaey, P. Chau, and J. Eldon, Eds. Piscataway, NJ: IEEE Press
-
M. Miranda, F. Catthoor, and H. De Man, "Address equation multiplexing for real time signal processing applications," VLSI Signal Processing, VII, J. Rabaey, P. Chau, and J. Eldon, Eds. Piscataway, NJ: IEEE Press, 1994, pp. 188-197.
-
(1994)
VLSI Signal Processing, VII
, pp. 188-197
-
-
Miranda, M.1
Catthoor, F.2
De Man, H.3
-
12
-
-
0030379869
-
ADOPT: Efficient hardware address generation in distributed memory architectures
-
M. Miranda, F. Catthoor, M. Janssen, and H. De Man, "ADOPT: Efficient hardware address generation in distributed memory architectures," in Proc. 9th ACM/IEEE Int. Symp. on System Synthesis, 1996, pp. 20-25.
-
(1996)
Proc. 9th ACM/IEEE Int. Symp. on System Synthesis
, pp. 20-25
-
-
Miranda, M.1
Catthoor, F.2
Janssen, M.3
De Man, H.4
-
13
-
-
0030651950
-
Architectural exploration and optimization for counter based hardware address generation
-
M. Miranda, M. Kaspar, F. Catthoor, and H. De Man, "Architectural exploration and optimization for counter based hardware address generation," in Proc. 8th ACM/IEEE European Design and Test Conf., 1997, pp. 293-298.
-
(1997)
Proc. 8th ACM/IEEE European Design and Test Conf.
, pp. 293-298
-
-
Miranda, M.1
Kaspar, M.2
Catthoor, F.3
De Man, H.4
-
14
-
-
0026174923
-
Cathedral-III: Architecture driven high-level synthesis for high throughput DSP applications
-
S. Note, W. Geurts, F. Catthoor, and H. De Man, "Cathedral-III: Architecture driven high-level synthesis for high throughput DSP applications," in Proc. 28th ACM/IEEE Design Automation Conf., 1991, pp. 597-602.
-
(1991)
Proc. 28th ACM/IEEE Design Automation Conf.
, pp. 597-602
-
-
Note, S.1
Geurts, W.2
Catthoor, F.3
De Man, H.4
-
15
-
-
0026997849
-
Time constrained allocation and assignment techniques for high throughput signal processing
-
W. Geurts, F. Catthoor, and H. De Man, "Time constrained allocation and assignment techniques for high throughput signal processing," in Proc. 29th ACM/IEEE Design Automation Conf., 1993, pp. 124-127.
-
(1993)
Proc. 29th ACM/IEEE Design Automation Conf.
, pp. 124-127
-
-
Geurts, W.1
Catthoor, F.2
De Man, H.3
-
16
-
-
0025386057
-
The high-level synthesis of digital systems
-
"The future of computer-aided design," Feb.
-
M. McFarland, A. Parker, and R. Camposano, "The high-level synthesis of digital systems," in Proc. IEEE, special issue on "The future of computer-aided design," vol. 78, no. 2, pp. 301-318, Feb. 1990.
-
(1990)
Proc. IEEE
, vol.78
, Issue.2 SPEC. ISSUE
, pp. 301-318
-
-
McFarland, M.1
Parker, A.2
Camposano, R.3
-
17
-
-
0029235762
-
Behavioral synthesis methodology for HDL-based specification and validation
-
D. Knapp, T. Ly, D. MacMillen, and R. Miller, "Behavioral synthesis methodology for HDL-based specification and validation," in Proc. 32nd ACM/IEEE Design Automation Conf., 1995.
-
(1995)
Proc. 32nd ACM/IEEE Design Automation Conf.
-
-
Knapp, D.1
Ly, T.2
MacMillen, D.3
Miller, R.4
-
18
-
-
0030675753
-
Array placement for storage size reduction in embedded multimedia systems
-
E. De Greef, F. Catthoor, and H. De Man, "Array placement for storage size reduction in embedded multimedia systems," in Proc. Int. Conf. Application-specific Systems, Architectures and Processors, 1997, pp. 66-75.
-
(1997)
Proc. Int. Conf. Application-specific Systems, Architectures and Processors
, pp. 66-75
-
-
De Greef, E.1
Catthoor, F.2
De Man, H.3
-
19
-
-
0024888769
-
Synthesis of address generators
-
D. Grant, P. Denyer, and I. Finlay, "Synthesis of address generators," in Proc. IEEE Int. Conf. Computer Aided Design, 1989, pp. 116-119.
-
(1989)
Proc. IEEE Int. Conf. Computer Aided Design
, pp. 116-119
-
-
Grant, D.1
Denyer, P.2
Finlay, I.3
-
20
-
-
33747778312
-
Design of a voice coder with the cathedral-II silicon compiler
-
B. Vanhoof, I. Bolsens, S. De Troch, L. Philips, J. Vanhoof, and H. De Man, "Design of a voice coder with the cathedral-II silicon compiler," in Proc. the User Forum and EuroASIC Prizes, 1993, pp. 150-153.
-
(1993)
Proc. the User Forum and EuroASIC Prizes
, pp. 150-153
-
-
Vanhoof, B.1
Bolsens, I.2
De Troch, S.3
Philips, L.4
Vanhoof, J.5
De Man, H.6
-
21
-
-
33747767125
-
-
Ph.D. thesis, Université de Rennes I, Rennes, France, Jan.
-
D. Chillet, "Méthodologie de conception architecturale des mémoires pour circuits dédíes au traitement du signal," Ph.D. thesis, Université de Rennes I, Rennes, France, Jan. 1997.
-
(1997)
Méthodologie de Conception Architecturale des Mémoires Pour Circuits Dédíes au Traitement du Signal
-
-
Chillet, D.1
-
22
-
-
0004072686
-
-
Reading, MA: Addison-Wesley
-
A. Aho, R. Sethi, and J. Ullman, "Compilers: Principles, techniques and tools." Reading, MA: Addison-Wesley, 1986.
-
(1986)
Compilers: Principles, Techniques and Tools
-
-
Aho, A.1
Sethi, R.2
Ullman, J.3
-
23
-
-
0028015521
-
A specification invariant technique for operation cost minimization in flow-graphs
-
J. M. Janssen, F. Catthoor, and H. De Man, "A specification invariant technique for operation cost minimization in flow-graphs," in Proc. 7th ACM/IEEE Int. Symp. on High-Level Synthesis, 1994, pp. 146-157.
-
(1994)
Proc. 7th ACM/IEEE Int. Symp. on High-Level Synthesis
, pp. 146-157
-
-
Janssen, J.M.1
Catthoor, F.2
De Man, H.3
-
24
-
-
0029214850
-
Beyond induction variables: Detecting and classifying sequences using a demand-driven SSA form
-
Jan.
-
M. Gerleck, E. Stoltz, and M. Wolfe, "Beyond induction variables: Detecting and classifying sequences using a demand-driven SSA form," ACM Trans. Programming Languages, Syst., vol. 17, no. 1, pp. 85-122, Jan. 1995.
-
(1995)
ACM Trans. Programming Languages, Syst.
, vol.17
, Issue.1
, pp. 85-122
-
-
Gerleck, M.1
Stoltz, E.2
Wolfe, M.3
-
25
-
-
0029780879
-
A specification invariant technique for regularity improvement between flow-graph clusters
-
J. M. Janssen, F. Catthoor, and H. De Man, "A specification invariant technique for regularity improvement between flow-graph clusters," in Proc. 7th ACM/IEEE European Design and Test Conf., 1996, pp. 138-143.
-
(1996)
Proc. 7th ACM/IEEE European Design and Test Conf.
, pp. 138-143
-
-
Janssen, J.M.1
Catthoor, F.2
De Man, H.3
-
26
-
-
0003512391
-
-
Boston, MA: Kluwer Academic
-
W. Geurts, F. Catthoor, S. Vernalde, and H. De Man, "Accelerator data-paths synthesis for high-throughput signal processing applications." Boston, MA: Kluwer Academic, 1996.
-
(1996)
Accelerator Data-paths Synthesis for High-throughput Signal Processing Applications
-
-
Geurts, W.1
Catthoor, F.2
Vernalde, S.3
De Man, H.4
-
27
-
-
52549114724
-
-
A. Chandrakasan and R. Brodersen Eds. Piscataway, NJ: IEEE Press
-
F. Catthoor, S. Wuytack, E. De Greef, F. Franssen, L. Nachtergaele, and H. De Man, "System-level transformations for low-power data transfer and storage in low-power CMOS design," A. Chandrakasan and R. Brodersen Eds. Piscataway, NJ: IEEE Press, 1998, pp. 609-618.
-
(1998)
System-level Transformations for Low-power Data Transfer and Storage in Low-power CMOS Design
, pp. 609-618
-
-
Catthoor, F.1
Wuytack, S.2
De Greef, E.3
Franssen, F.4
Nachtergaele, L.5
De Man, H.6
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