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Volumn 6, Issue 4, 1998, Pages 677-686

High-level address optimization and synthesis techniques for data-transfer-intensive applications

Author keywords

Arithmetic; Clustering; High performance; Memory; Partitioning; Tradeoffs

Indexed keywords

DATA PROCESSING; DATA STORAGE EQUIPMENT; DIGITAL ARITHMETIC;

EID: 0032295394     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.736141     Document Type: Article
Times cited : (44)

References (27)
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    • Address equation multiplexing for real time signal processing applications
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    • Cathedral-III: Architecture driven high-level synthesis for high throughput DSP applications
    • S. Note, W. Geurts, F. Catthoor, and H. De Man, "Cathedral-III: Architecture driven high-level synthesis for high throughput DSP applications," in Proc. 28th ACM/IEEE Design Automation Conf., 1991, pp. 597-602.
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    • Note, S.1    Geurts, W.2    Catthoor, F.3    De Man, H.4
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    • Time constrained allocation and assignment techniques for high throughput signal processing
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    • The high-level synthesis of digital systems
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    • (1990) Proc. IEEE , vol.78 , Issue.2 SPEC. ISSUE , pp. 301-318
    • McFarland, M.1    Parker, A.2    Camposano, R.3
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    • Beyond induction variables: Detecting and classifying sequences using a demand-driven SSA form
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    • M. Gerleck, E. Stoltz, and M. Wolfe, "Beyond induction variables: Detecting and classifying sequences using a demand-driven SSA form," ACM Trans. Programming Languages, Syst., vol. 17, no. 1, pp. 85-122, Jan. 1995.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.