Address Generation for Memories Containing Multiple Arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 5, 1998, Pages 377-385

  Schmit, Herman ^a   Thomas Jr , Donamld E ^a,b  

^a Department of IEEE ^*  (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Arrays, compilers (silicon); Digital arithmetic; High level synthesis; Memory management; Number theoretic transforms

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARRAYS; DIGITAL ARITHMETIC; ELECTRIC NETWORK SYNTHESIS; MATHEMATICAL TRANSFORMATIONS; STORAGE ALLOCATION (COMPUTER);

ADDER FREE ADDRESS GENERATION;

DATA STORAGE EQUIPMENT;

EID: 0032068881     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.703919     Document Type: Article

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