Address code and arithmetic optimizations for embedded systems

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 619-624

  Ramanujam, J ^a   Krishnamurthy, S ^a   Hong, J ^a   Kandemir, M ^b  

^a LOUISIANA STATE UNIVERSITY   (United States)

^b The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER AIDED DESIGN; COST REDUCTION; DESIGN; IMAGE PROCESSING; PROGRAM COMPILERS;

ADDRESS COMPUTATION; ADDRESS GENERATION; COMPILER TECHNOLOGY; MEMORY LOCATIONS; MEMORY PERFORMANCE; REGISTER PRESSURE; STATE OF THE ART; SUCCESSIVE ITERATION;

EMBEDDED SYSTEMS;

EID: 84962226456     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.995005     Document Type: Conference Paper

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