Microarchitecture evaluation with floorplanning and interconnect pipelining

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages

  Jagannathan, Ashok ^a   Yang, Hannah Honghua ^b   Konigsfeld, Kris ^b   Milliron, Dan ^b   Mohan, Mosur ^b   Romesis, Michail ^a   Reinman, Glenn ^a   Cong, Jason ^a  

^a University of California   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PATHS; EVALUATION METHODOLOGIES; FLOOR-PLANNING; FREQUENCY-SCALING; INTERCONNECT DELAY; INTERCONNECT PIPELINING; MICRO ARCHITECTURES; MICRO-ARCHITECTURE DESIGN; NANO-METER REGIMES; PERFORMANCE SENSITIVITY; TARGET FREQUENCIES;

COMPUTER AIDED DESIGN; WIRE;

OPTIMIZATION;

EID: 33750838127     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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