3D CBL: An efficient algorithm for general 3-dimensional packing problems

Midwest Symposium on Circuits and Systems

Volumn 2005, Issue , 2005, Pages 1079-1082

  Ma, Yuchun ^a   Hong, Xianlong ^a   Dong, Sheqin ^a   Cheng, C K ^b  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT LAYOUT; PACKING; PROBLEM SOLVING; TOPOLOGY; VLSI CIRCUITS;

3-DIMENSIONAL CORNER BLOCK LIST (3D CBL); FLOORPLAN REPRESENTATION;

ALGORITHMS;

EID: 33847097921     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2005.1594292     Document Type: Conference Paper

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