A comprehensive analysis of off-state stress in drain extended PMOS transistors: Theory and characterization of parametric degradation and dielectric failure

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2008, Pages 566-574

  Varghese, D ^a   Reddy, V ^b   Shichijo, H ^b   Mosher, D ^b   Krishnan, S ^b   Alam, M A ^a  

^a PURDUE UNIVERSITY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PARAMETRIC DEGRADATION; PMOS TRANSISTORS; RELIABILITY PHYSICS;

CHARGE CARRIERS; CIVIL AVIATION; DEGRADATION; FAILURE ANALYSIS; GATE DIELECTRICS; GATES (TRANSISTOR); RELIABILITY; STRESSES; TRANSISTORS;

MOSFET DEVICES;

EID: 51549096203     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2008.4558946     Document Type: Conference Paper

References (30)

1. C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terril, "Hot-electron-induced MOSFET degradation - model, monitor, and improvement," IEEE Journal of Solid-State Circuits, vol. SC-20, pp. 295-305, 1985.
2. D. J. Dumin, R. S. Scott, and R. Subramoniam, "A model relating wearout induced physical changes in thin oxides to the statistical description of breakdown," in Proc. Int. Reliability Physics Symposium, 1993, pp. 285-292.
3. S. Pae, M. Agostinelli, G. Curello, S. Lau, S. Ramey, and M. Alavi, "New gate oxide wear-out model for accurate device lifetime projections on vertical drain NMOSFET," in Integrated Reliability Workshop Final Report, 2004, pp. 19-22.
4. T. Furukawa, D. Turner, S. Mittl, M. Maloney, R. Serafin, W. Clark, J. Bialas, L. Longenbach, and J. Howard, "Accelerated gate-oxide breakdown in mixed-voltage I/O circuits," in Proc. Int. Reliability Physics Symp., 1997, pp. 169-173.
5. E. Wu, E. Nowak, and W. Lai, "Off-state mode TDDB reliability for ultra-thin gate oxides: New methodology and the impact of oxide thickness scaling," in Proc. Int. Reliability Physics Sumposium, 2004, pp. 84-94.
6. B. Kaczer, F. Crupi, R. Degraeve, P. Roussel, C. Ciofi, and G. Groeseneken, "Observation of hot-carrier-induced nFET gate-oxide breakdown in dynamically stressed CMOS circuits," in Proc. Int. Electron Device Meeting, 2002, pp. 171-174.
7. D. Varghese, H. Kufluoglu, V. Reddy, H. Shichijo, S. Krishnan, and M. A. Alam, "Universality of off-state degradation in drain extended NMOS transistors," in Proc. Int. Electron Device Meeting, 2006, pp. 751-754.
8. D. Varghese, H. Kufluoglu, V. Reddy, H. Shichijo, D. Mosher, S. Krishnan, and M. A. Alam, "Multi-probe Two-Dimensional Mapping of Off-State Degradation in DeNMOS Transistors: How and Why Interface Damage Predicts Gate Dielectric Breakdown," in Proc. Int. Electron Device Meeting, 2007, pp. s 19.4.
9. D. Varghese, H. Kufluoglu, V. Reddy, H. Shichijo, D. Mosher, S. Krishnan, and M. A. Alam, "Off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown," IEEE Trans. on Electron Devices, vol. 54, pp. 2669-2678, 2007.
10. D. Ielmini, A. Ghetti, S. Beltrami, A. S. Spinelli, A. L. Lacaita, and A. Visconti, "Experimental and Monte Carlo analysis of drain-avalanche hot-hole injection for reliability optimization in Flash memories," in Int. Electron Devices Meeting, 2003, pp. 157-160.
11. D. Varghese, S. Mahapatra, and M. A. Alam, "Hole energy dependent interface trap generation in MOSFET Si/SiO2 interface," IEEE Electron Device Letters, vol. 26, pp. 572-574, 2005.
12. S. Mahapatra, D. Saha, D. Varghese, and P. B. Kumar, "On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress," IEEE Trans. on Electron Devices, vol. 53, pp. 1583-1592, 2006.
13. D. S. Ang and C. H. Ling, "A unified model for the self-limiting hot-carrier degradation in LDD nMOSFET's," IEEE Trans. on Electron Devices, vol. 45, pp. 149-159, 1998.
14. J.-S. Goo, H. Shin, H. Hwang, D.-G. Kang, and D.-H. Ju, "Physical Analysis for Saturation Behavior of Hot-Carrier Degradation in Lightly Doped Drain N-Channel Metal-Oxide-Semiconductor Field Effect Transistors," Jpn. J. Appl. Phys., vol. 33, pp. 606-611, 1994.
15. J. C. Mitros, C.-y. Tsai, H. Shichijo, K. Kunz, A. Morton, D. Goodpaster, D. Mosher, and T. R. Efland, "High-voltage drain extended MOS transistors for 0.18-um logic CMOS process," IEEE Trans. on Electron Devices, vol. 48, pp. 1751-1755, Aug. 2001.
16. E. Wu and E. Nowak, "Voltage-splitting technique for reliability evaluation of off-state mode of MOSFETs in ultrathin gate," IEEE Electron Device Letters, vol. 25, pp. 414-416, 2004.
17. D. J. Massey, J. P. R. David, and G. J. Rees, "Temperature dependence of impact ionization in submicrometer silicon devices," IEEE Trans. on Electron Devices, vol. 53, pp. 2328-2334, 2006.
18. "User guide, MEDICI, Version 2003.06," 2003.
19. J. D. Bude, M. R. Pinto, and R. K. Smith, "Monte Carlo simulation of the CHISEL flash memory cell," IEEE Trans. on Electron Devices, vol. 47, pp. 1873-1881, 2000.
20. W. K. Chim, S. E. Leang, and D. S. H. Chan, "Extraction of metal-oxide-semiconductor field-effect-transistor interface state and trapped charge spatial distributions using a physics-based algorithm," J. Appl. Phys., vol. 81, pp. 1992-2001, 1997.
21. H. Kufluoglu and M. A. Alam, "A geometrical unification of the theories of NBTI and HCI time-exponents and Its Implications for ultra-scaled planar and surround-gate MOSFETS," in Proc. Int. Electron Device Meeting, 2004, pp. 113-116.
22. M. A. Alam, "A critical examination of the mechanics of dynamic NBTI for PMOSFETs," in Int. Electron Devices Meeting, 2003, pp. 345-348.
23. G. Groeseneken and H. E. Maes, "Basics and applications of charge pumping in submicron MOSFETs," Microelectronics Reliability, vol. 38, pp. 1379-1389, 1998.
24. R. Degraeve, G. Groeseneken, R. Bellens, M. Depas, and H. E. Maes, "A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides," in Int. Electron Devices Meeting, 1995, pp. 863-866.
25. J. Sune, "New physics-based analytic approach to the thin-oxide breakdown statistics," IEEE Electron Device Letters, vol. 22, pp. 296-298, 2001.
26. Y. Maneglia and Bauza, "Extraction of slow oxide trap concentration profiles in metal-oxide-semiconductor transistors using the charge pumping method," Journal of Applied Physics, vol. 79, pp. 4187-4192, 1996.
27. R. Degraeve, B. Kaczer, A. D. Keersgieter, and G. Groeseneken, "Relation between breakdown mode and location in short-channel nMOSFETs and its impact on reliability specifications," IEEE Trans. on Device and Materials Reliability, vol. 1, pp. 163-169,2001.
28. M. A. Alam, D. Monroe, B. E. Weir, and P. J. Silverman, "Theory of "current-ratio" method for oxide reliability: proposal and validation of a new class two-dimensional breakdown-spot characterization techniques," in Int. Electron Devices Meeting, 2005, pp. 415-418.
29. M. A. Alam, D. Varghese, and B. Kaczer, "Theory of Breakdown Position Determination by Voltage- and Current Ratio Methods," IEEE Trans. on Electron Devices. (In Review).
30. A. T. Krishnan and P. E. Nicollian, "Analytic Extension of the Cell-Based Oxide Breakdown Model to Full Percolation and its Implications," in Int. Reliability Physics Symposium, 2007, pp. 232-239.