Multi-probe two-dimensional mapping of off-state degradation in DeNMOS transistors: How and why interface damage predicts gate dielectric breakdown

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 505-508

  Varghese, D ^a   Kufluoglu, H ^a   Reddy, V ^b   Shichijo, H ^b   Mosher, D ^b   Krishnan, S ^b   Alam, M A ^a  

^a PURDUE UNIVERSITY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN; ELECTRIC CURRENTS; ELECTRON DEVICES; GATE DIELECTRICS; GATES (TRANSISTOR); SULFATE MINERALS; SURFACE CHEMISTRY; TRANSISTORS; TWO DIMENSIONAL;

CHARGE PUMPING; DAMAGE LOCATIONS; DIELECTRIC BREAKDOWN; GATE DIELECTRIC BREAKDOWN; INTERFACE AND BULK TRAPS; NMOS TRANSISTORS; OFF-STATE STRESS; PERCOLATION MODELS; PHYSICAL MECHANISMS; TIME CONSUMING; TWO-DIMENSIONAL MAPPINGS; WEIBULL SLOPE;

MOSFET DEVICES;

EID: 50249129667     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418985     Document Type: Conference Paper

References (11)

1. K. Nakamura et al., BCTM00, p94.
2. S. Xu et al., ISPSD03, p190.
3. J. Mitros et al., TED, 48, p1751, 2001.
4. S. Pae et al., IRW Final Report, p19, 2004.
5. M. A. Alam et al., IEDM05, p415.
6. D. Varghese et al., IEDM06, p751.
7. A. Asenov et al., Microelectronic Engineering, 15, p445, 1991.
8. W. Chim et al., JAP, 81, p1992, 1997.
9. Y. Maneglia et al., JAP, 79, p4187, 1996.
10. R. Degraeve et al., IEDM 95, p863.
11. J. Suñé, EDL, 22, p296, 2001.