High-voltage drain extended MOS transistors for 0.18-μm logic CMOS process

IEEE Transactions on Electron Devices

Volumn 48, Issue 8, 2001, Pages 1751-1755

  Mitros, Jozef C ^a,b   Tsai, Chin Yu ^a,b   Shichijo, Hisashi ^a,b   Kunz, Keith ^a,b   Morton, Alec ^b   Goodpaster, Doug ^b   Mosher, Dan ^a,b   Efland, Taylor R ^a,b  

^a IEEE   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Drain extended MOSFETs; High voltage techniques; Integrated circuit manufacture; Integrated circuits; MOSFETs

Indexed keywords

DRAIN EXTENDED MOSFETS; SOFTWARE PACKAGE MEDICI; SOFTWARE PACKAGE SUPREME;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC BREAKDOWN; INTEGRATED CIRCUIT MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES;

MOSFET DEVICES;

EID: 0035425125     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.936703     Document Type: Conference Paper

References (2)

1. A scaled 1.8 V, 0.18 μm gate length CMOS technology
2. A sub-0.18-μm gate length CMOS technology for high performance (1.5 V) and lower power