New gate oxide wear-out model for accurate device lifetime projections on vertical drain NMOSFET

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2004, Pages 19-22

  Pae, S ^a   Agostinelli, M ^a   Curello, G ^a   Lau, S ^a   Ramey, S ^a   Alavi, M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; GATES (TRANSISTOR); LEAKAGE CURRENTS; MATHEMATICAL MODELS; RELIABILITY; SEMICONDUCTOR DEVICE STRUCTURES;

DRAIN CURRENT; GATE LEAKAGE CURRENT; HOT CARRIER DEGRADATION EFFECT; TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB);

MOSFET DEVICES;

EID: 21644462708     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. Brand et al., US patent #6,287,908 and #6,172,401.
2. V. O'Donovan et al., IRPS, pp. 174-177, 2000.
3. D. Brisbin et al., IRPS, pp. 608-609, 2003.
4. P. Moens et al., IRPS, pp. 214-221, 2003.
5. S. Thompson et al., IEDM, pp. 61-64, 2002.
6. E. Wu et al., IEEE TED, Vol. 49, No. 12, pp. 2244-2253, 2002.