Comparison of a timing-error tolerant scheme with a traditional re-transmission mechanism for networks on chips

2006 International Symposium on System-on-Chip, SOC

Volumn , Issue , 2006, Pages

  Murali, Srinivasan ^a   Tamhankar, Rutuparna ^b   Angiolini, Federico ^c   Pullini, Antonio ^c   Atienza, David ^d   Benini, Luca ^c   De Micheli, Giovanni ^d  

^a STANFORD UNIVERSITY   (United States)

^b SUN MICROSYSTEMS   (United States)

^c UNIVERSITY OF BOLOGNA   (Italy)

^d EPFL   (Switzerland)

Author keywords

Double sampling; Networks on chips; Retransmission; Systems on chips; Timing errors

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; MECHANISMS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; TIME DELAY; TIME MEASUREMENT; TIME VARYING SYSTEMS; WIRE;

CYCLE-ACCURATE; DESIGN METHODOLOGIES; DOUBLE SAMPLING; DYNAMIC RECOVERY; ERROR RECOVERY MECHANISMS; ERROR SYSTEMS; ERROR-RECOVERY; ERROR-TOLERANT; INTERCONNECT WIRES; INTERNATIONAL SYMPOSIUM; NETWORK-ON-CHIP DESIGN; NETWORKS ON CHIPS; NOISE SOURCES; ON-CHIP WIRES; RETRANSMISSION; RTL MODELS; SYSTEM ON CHIPS; SYSTEMS ON CHIPS; TECHNOLOGY SCALING; TIMING DELAYS; TIMING ERRORS; TRANSMISSION MECHANISMS; VIRTUAL PLATFORM;

COMPUTER SYSTEM RECOVERY;

EID: 50049127076     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSOC.2006.321983     Document Type: Conference Paper

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