Going beyond worst-case specs with TEAtime

Computer

Volumn 37, Issue 3, 2004, Pages 51-56

  Uht, Augustus K ^a  

^a The University of Rhode Island   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BUFFER STORAGE; COMPUTER AIDED DESIGN; COMPUTER HARDWARE; COMPUTER SYSTEMS; DIGITAL TO ANALOG CONVERSION; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; INDUCTANCE; MICROCONTROLLERS; MICROPROCESSOR CHIPS; TIMING CIRCUITS;

DIGITAL SYSTEM DESIGN; POWER REDUCTION; TIMING-ERROR-AVOIDANCE METHOD; TRACKING LOGIC;

SYSTEMS ANALYSIS;

EID: 1842477897     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2004.1274004     Document Type: Article

References (10)

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2. A.K. Uht, "Achieving Typical Delays in Synchronous Systems via Timing Error Toleration," tech. report 032000-0100, Dept. Electrical and Computer Eng., Univ. of Rhode Island, 10 Mar. 2000; www.ele.uri/edu/~uht.
3. D. Ernst et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," Proc. 2003 Int'l Symp. Microarchitecture, IEEE CS Press 2003, pp. 7-18.
4. A. Merchant et al., "Analysis of a Control Mechanism for a Variable Speed Processor," IEEE Trans. Computers, vol. 45, no. 7, 1996, pp. 968-976.
5. AMD Staff, "AMD Power Now! Technology Brief," Advanced Micro Devices, Inc., 2002; www.amd.com/us-en/assets/content_type/DownloadableAssets/Power_Now2.pdf.
6. Intel Staff, "Intel Low-Power Technologies," Intel Corp., 2003; www.intel.com/ebusiness/products/related_mobile/wp021601_sum.htm?iid=ipp_battery +press_lowpow.
7. A. E. Sjogren and C.J. Myers, "Interfacing Synchronous and Asynchronous Modules within a High-Speed Pipeline," Proc. 17th Conf. Advanced Research in VLSI (ARVLSI 97), IEEE CS Press, 1997, pp. 47-61.
8. T. D. Burd et al., "A Dynamic Voltage Scaled Microprocessor System," IEEE J. Solid-State Circuits, vol. 35, no. 11, 2000, pp. 1571-1580.
9. A.J. Martin, "Design of an Asynchronous Microprocessor," tech. report CS-TR-89-02, Computer Science Dept., California Inst. of Technology, 1989.
10. E. Grochowski, D. Ayers, and V. Tiwari, "Microarchitectural di/dt Control," IEEE Design & Test of Computers, May-June 2003, pp. 40-47.