메뉴 건너뛰기




Volumn , Issue , 2004, Pages 319-324

Reducing pipeline energy demands with local DVS and dynamic retiming

Author keywords

Dynamic retiming with global DVS; Local DVS; Razor

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CONVERTERS; ELECTRONIC EQUIPMENT; ENERGY UTILIZATION; ERROR ANALYSIS; NETWORKS (CIRCUITS); PIPELINES; VOLTAGE CONTROL;

EID: 15044362543     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013313     Document Type: Conference Paper
Times cited : (22)

References (17)
  • 2
    • 0036469652 scopus 로고    scopus 로고
    • SimpleScalar: An infrastructure for computer system modeling
    • February
    • T. Austin, E. Larson, D. Ernst. "SimpleScalar: an Infrastructure for Computer System Modeling", IEEE Computer, 35 (2), February 2002.
    • (2002) IEEE Computer , vol.35 , Issue.2
    • Austin, T.1    Larson, E.2    Ernst, D.3
  • 6
    • 84860106234 scopus 로고    scopus 로고
    • Synopsis Corporation, "PrimeTime", http://www.synopsys.com/products/analysis/analysis.html.
    • PrimeTime
  • 8
    • 0035311079 scopus 로고    scopus 로고
    • Power: A first class design constraint
    • April
    • T. Mudge. "Power: A first class design constraint", Computer, vol. 34, no. 4, April 2001, pp. 52-57.
    • (2001) Computer , vol.34 , Issue.4 , pp. 52-57
    • Mudge, T.1
  • 9
    • 0034315851 scopus 로고    scopus 로고
    • A dynamic voltage scaled microprocessor system
    • November
    • T. Burd. et, al "A Dynamic Voltage Scaled Microprocessor System", IEEE Journal of Solid-State Circuits, Vol 35, No. 11, November 2000.
    • (2000) IEEE Journal of Solid-state Circuits , vol.35 , Issue.11
    • Burd, T.1
  • 11
    • 0025554245 scopus 로고    scopus 로고
    • CheckTc and MinTc: Timing verification and optimal clocking of synchronous digital circuits
    • K. Sakallah, T. Mudge, and O. Olukotun. "checkTc and MinTc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits", 1990 IEEE.
    • 1990 IEEE
    • Sakallah, K.1    Mudge, T.2    Olukotun, O.3
  • 12
    • 0034758511 scopus 로고    scopus 로고
    • A socket interface for GALS using locally dynamic voltage scaling for rate-adaptive energy saving
    • T. Njølstad. et.al "A Socket Interface For GALS Using Locally Dynamic Voltage Scaling For Rate-Adaptive Energy Saving", IEEE 2001.
    • IEEE 2001
    • Njølstad, T.1
  • 13
    • 16244412780 scopus 로고    scopus 로고
    • Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor
    • Special Issue on Power-Aware Issue on the Top Picks from Microarchitecture Conference
    • M. Semeraro. et, al "Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor", IEEE Micro, Special Issue on Power-Aware Issue on the Top Picks from Microarchitecture Conference, Vol 36, No. 12.
    • IEEE Micro , vol.36 , Issue.12
    • Semeraro, M.1
  • 15
    • 0033717865 scopus 로고    scopus 로고
    • Clock rate versus IPC: The end of the road for conventional microarchitectures
    • V. Agarwal, M.S. Hrishikesh, S. Keckler, D. Burger, "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures", ISCA-2000.
    • ISCA-2000
    • Agarwal, V.1    Hrishikesh, M.S.2    Keckler, S.3    Burger, D.4
  • 16
    • 0036953769 scopus 로고    scopus 로고
    • Automatically characterizing large scale program behavior
    • October
    • T. Sherwood, E. Perelman, G. Hamerly and B. Calder, "Automatically Characterizing Large Scale Program Behavior", ASPLOS-X, October 2002.
    • (2002) ASPLOS-X
    • Sherwood, T.1    Perelman, E.2    Hamerly, G.3    Calder, B.4
  • 17
    • 0031212817 scopus 로고    scopus 로고
    • Supply and threshold voltage scaling for low power CMOS
    • August
    • R. Gonzalez, B. Gordon, and M. Horowitz, "Supply and Threshold Voltage Scaling for Low Power CMOS", IEEE JSSC, 32 (8), August 1997.
    • (1997) IEEE JSSC , vol.32 , Issue.8
    • Gonzalez, R.1    Gordon, B.2    Horowitz, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.