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Volumn 2004-January, Issue January, 2004, Pages 180-185

Architecting Voltage Islands in Core-Based System-on-a-Chip Designs

Author keywords

floorplanning; low power; multiple VDD< inf>; System on a Chip; voltage island

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BENCHMARKING; DESIGN; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; POWER ELECTRONICS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

EID: 84932170042     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2004.240892     Document Type: Conference Paper
Times cited : (28)

References (9)
  • 5
    • 0028711580 scopus 로고
    • A survey of power estimation techniques in vlsi circuits
    • Dec
    • F. N. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans. on VLSI Systems, vol. 2, no. 4, pp. 446-455, Dec. 1994.
    • (1994) IEEE Trans. on VLSI Systems , vol.2 , Issue.4 , pp. 446-455
    • Najm, F.N.1
  • 6
    • 84949784966 scopus 로고    scopus 로고
    • FAST-sp: A fast algorithm for block placement based on sequence pair
    • Jan
    • X. Tang and D. F. Wong, "FAST-SP: a fast algorithm for block placement based on sequence pair," in Proc. Asia South Pacific Design Automat. Conf., Jan. 2001, pp. 512-526.
    • (2001) Proc. Asia South Pacific Design Automat. Conf. , pp. 512-526
    • Tang, X.1    Wong, D.F.2
  • 7
    • 0030378255 scopus 로고    scopus 로고
    • VLSI module placement based on rectangle-packing by the sequence pair
    • Dec
    • H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence pair," IEEE Trans. on Computer-Aided Design, vol. 15, no. 12, pp. 1518-1524, Dec. 1996.
    • (1996) IEEE Trans. on Computer-Aided Design , vol.15 , Issue.12 , pp. 1518-1524
    • Murata, H.1    Fujiyoshi, K.2    Nakatake, S.3    Kajitani, Y.4
  • 8
    • 0036051050 scopus 로고    scopus 로고
    • Floorplanning with alignment and performance constraints
    • June
    • X. Tang and D. F. Wong, "Floorplanning with alignment and performance constraints," in Proc. Design Automat. Conf., June 2002, pp. 848-853.
    • (2002) Proc. Design Automat. Conf. , pp. 848-853
    • Tang, X.1    Wong, D.F.2
  • 9
    • 84860094561 scopus 로고    scopus 로고
    • IBM Corp
    • IBM Corp., "IBM platform-based design kit," http://www- 3.ibm.com/chips/products/asics/methodology/design kit.html.
    • IBM Platform-based Design Kit


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.