Thermal management of on-chip caches through power density minimization

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2005, Pages 283-293

  Ku, Ja Chun ^a   Ozdemir, Serkan ^a   Memik, Gokhan ^a   Ismail, Yehea ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE POWER REDUCTION; POWER DENSITY MINIMIZATION; THERMAL MANAGEMENT; THERMAL-AWARE ARCHITECTURE;

COMPUTER ARCHITECTURE; ENERGY UTILIZATION; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; OPTIMIZATION; THERMAL EFFECTS;

CACHE MEMORY;

EID: 33749396826     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2005.36     Document Type: Conference Paper

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