PADded cache: a new fault-tolerance technique for cache memories

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 440-445

  Shirvani, Philip P ^a   McCluskey, Edward J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; COMPUTER SIMULATION; ESTIMATION; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC CIRCUITS;

ASSOCIATIVE CACHE; PROGRAMMABLE ADDRESS DECODER;

BUFFER STORAGE;

EID: 0032639192     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (18)