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Volumn , Issue , 2006, Pages 453-456

Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories

Author keywords

[No Author keywords available]

Indexed keywords

SEARCH ACCESS TIME; SELF REFERENCED SENSING SCHEME (SRSS); TIMING UNCERTAINTY;

EID: 39049170058     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320819     Document Type: Conference Paper
Times cited : (25)

References (7)
  • 1
    • 54949151196 scopus 로고    scopus 로고
    • Approach for physical design in sub-100 nm era
    • H. Masuda, S. Okawa, M. Aoki "Approach for physical design in sub-100 nm era," ISCAS 2005, Vol. 6, pp. 5934-5937.
    • (2005) ISCAS , vol.6 , pp. 5934-5937
    • Masuda, H.1    Okawa, S.2    Aoki, M.3
  • 2
    • 16244389977 scopus 로고    scopus 로고
    • Process and environmental variation: Impacts on ASIC timing
    • P.S. Zuchowski, P.A. Habitz, J.D. Hayes, and J.H. Oppold, "Process and environmental variation: impacts on ASIC timing," ICCAD-2004, pp. 336-342
    • (2004) ICCAD , pp. 336-342
    • Zuchowski, P.S.1    Habitz, P.A.2    Hayes, J.D.3    Oppold, J.H.4
  • 3
    • 0035307453 scopus 로고    scopus 로고
    • A 1-V 128-kb Four-Set-Associative CMOS Cache Memory Using Wordline-Qriented Tag Compare(WLOTC) Structure with Content-Addressable Memory (CAM) 10-Transistor Tag Cell
    • Apr
    • P. Lin and J. Kuo,"A 1-V 128-kb Four-Set-Associative CMOS Cache Memory Using Wordline-Qriented Tag Compare(WLOTC) Structure with Content-Addressable Memory (CAM) 10-Transistor Tag Cell," IEEE JSSC, Vol. 36, No. 4, pp. 666-676, Apr.2001.
    • (2001) IEEE JSSC , vol.36 , Issue.4 , pp. 666-676
    • Lin, P.1    Kuo, J.2
  • 4
    • 0037245512 scopus 로고    scopus 로고
    • A Ternary Content-Addressable Memory (TCAM) Based on 4T Static Storage and Including a Current-Race Sensing Scheme
    • Jan
    • I. Arsovski, T. Chandler, A. Sheikholeslami,"A Ternary Content-Addressable Memory (TCAM) Based on 4T Static Storage and Including a Current-Race Sensing Scheme," IEEE JSSC, Jan, 2003.
    • (2003) IEEE JSSC
    • Arsovski, I.1    Chandler, T.2    Sheikholeslami, A.3
  • 5
    • 0030674247 scopus 로고    scopus 로고
    • Power reduction in large fan-in CMOS gates in logic arrays using selective precharge
    • C. A. Zukowski and S.-Y. Wang, "Power reduction in large fan-in CMOS gates in logic arrays using selective precharge," Great Lakes Symposium on VLSI, 1997, pp. 83-87
    • (1997) Great Lakes Symposium on VLSI , pp. 83-87
    • Zukowski, C.A.1    Wang, S.-Y.2
  • 6
    • 0035369412 scopus 로고    scopus 로고
    • A design for high-speed low-power CMOS fully parallel content-addressable memory macros
    • June
    • H. Miyatake, M. Tanaka, and Y. Mori, "A design for high-speed low-power CMOS fully parallel content-addressable memory macros," IEEE JSSC, Vol 36, No, 6, pp. 956-968, June 2001.
    • (2001) IEEE JSSC , vol.36 , Issue.6 , pp. 956-968
    • Miyatake, H.1    Tanaka, M.2    Mori, Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.